Vivado從此開始（第2版）課件 26-UltraFast-Design(4)-Timing-Constraint- 30-UltraFast-Design(8)-Impl-Strategies

Lauren

GaoUltraFastDesign:Timing

ConstraintDefiningTimingConstraintsinFour

StepsCreate

ClocksPrimaryGeneratedUncertaintycreate_clockcreate_generated_clockset_sytem_jitterset_input_jitterset_clock_uncertaintyset_clock_latencyReportsClock

NetworksCheck

Timingset_input_delayset_output_delayset_clock_groupsset_false_pathset_false_pathset_min/max_delayset_multicycle_pathset_case_analysisset_disable_timingI/O

DelaySystemSource

SYNClock

GroupsCDCASYNExclusiveTiming

Exce.IgnoreMax/minReportsCheck

TimingReport

TimingReportsClock

InteractionCheck

TimingReportsTiming

SummaryReport

Timing1234Createclocksanddefineclock

interactionsFour-step

guidelineSetinputandoutput

delaysBewareofcreatingincorrectHOLD

violationsSettiming

exceptionsLessis

more!BewareofcreatingincorrectHOLD

violationsUsereportcommandstovalidateeach

stepMethodtoCreateGood

ConstraintsPage

3ForSDC-basedtimers,clocksonlyexistifyoucreate

themUsecreate_clock

forprimaryclocksClockspropagateautomaticallythroughclocking

modulesMMCMandPLLoutputclocksareautomatically

generatedGigabittransceiversarenotsupported.Createthem

manually.Usecreate_generated_clock

forinternalclocks(ifneeded)Allinter-clockpathsareevaluatedby

defaultClockGround

RulesPage

4don’tcreate_clock

herecreate_clockhereFourStepsforCreating

ClocksClockPeriodWaveformAttributesSourcessys_clk10.000{0.000

5.000}P{sys_clk}pll0/clkfbout10.000{0.000

5.000}P,G{pll0/plle2_adv_inst/CLKFBOUT}pll0/clkout02.500{0.000

1.250}P,G{pll0/plle2_adv_inst/CLKOUT0}pll0/clkout110.000{0.000

5.000}P,G{pll0/plle2_adv_inst/CLKOUT1}Page

5Step

1Usecreate_clock

forallprimaryclocksontoplevelportsRunthedesign(synthesis)oropennetlist

designStep

2Run

report_clocksStudythereporttoverifyperiod,phaseand

propagationApplycorrectionstoyourconstraints(if

needed)AttributesP:

PropagatedG:GeneratedStep

3Evaluatetheclockinteractionusing

report_clock_interactionBEWARE:Allinter-clockpathsareconstrainedby

default!Markinter-clockpaths(ClockDomainCrossing)as

asynchronousMakesureyoudesignedproperCDC

synchronizersUseset_clock_groups

(preferredmethodtoset_false_path)BEWARE:Thisoverridesanyset_max_delay

constraints!Doyouhaveunconstrained

objects?Findoutwith

check_timingStep

4Run

report_clock_networksYouwantthedesigntohavecleanclocklineswithout

logicTip:UseclockgatingoptioninsynthesistoremoveLUTsontheclock

lineFourStepsforCreatingClocks

(continued)Page

6WhatisthePrimary

ClockPrimary

ClockJitterInputjitter:

set_input_jitterSystemjitter:set_system_jitterAdditional

uncertainty–

set_clock_uncertaintyAddextramarginthetimingpathsofaclockorbetweentwo

clocksThisisalsothebestandsafestwaytoover-constrainaportionofadesignwithoutmodifyingtheactualclockedgesandtheoverallclocks

relationshipsAdjustingClock

CharacteristicsConstraints

ValidationConstraints

CreationConstraints

Validation#Checkifthereareendpointsthataremissinga

constraintcheck_timingcheck_timing–override_defaults

no_clock#Determinethesourceofmissing

clockscheck_timingreport_clock_networks#Validateclock

characteristicsreport_clocksreport_property[get_clocks

wbClk]SystemLevel

Perspective–TheI/Opathsaremodeledlikeanyotherreg-to-regpathsbytheVivadoDesignSuitetimingengine,exceptthatpartofthepathislocatedoutsidetheFPGAdeviceandneedstobedescribedbythe

userConstrainingInputandOutput

PortsUsealimitednumberoftimingexceptionsandkeepthem

simplewheneverpossible–Theruntimeofthecompilationflowwillsignificantlyincreasewhenmanyexceptionsareused,especiallywhentheyareattachedtoalargenumberofnetlist

objectsThemorespecifictheconstraint,thehigherthe

priorityTimingExceptions

Guidelinesset_false_path-from[get_portsdin]-to

[all_registers]set_false_path-from[get_portsdin]set_false_path-from[get_portsdin]-to[get_cells

blockA/config_reg[*]]set_max_delay-from[get_clocksclkA]-to[get_pinsinst0/D]12set_max_delay-from[get_clocksclkA]-to[get_clocksclkB]

10WinYouhaveadesignwithtwoclockscomingonportscalledwbClkand

bftClkwbClkisa100MHzclock,with150psofjitteranda60/40duty

cyclewithinthewbClkclockdomain,setupclockuncertainty213

psbftClkisa200MHzclock,with30psofjitteranda50/50duty

cycleThefallingedgeofbftClkisalignedwiththerisingedgeof

wbClkThedesignwasdesignedtohandleallCDCpathscorrectly.AssumethatallCDCpathsderivedfromthetwoprimaryclockscanbe

ignoredExampleExample

SolutionsSolutionscreate_clock-namewbClk-period10.0-waveform{0.06.0}[get_portswbClk]set_input_jitterwbClk

0.15set_clock_uncertainty-setup0.213[get_clocks

wbClk]create_clock-namebftClk-period5.0-waveform{2.55}[get_ports

bftClk]set_input_jitterbftClk

0.03set_clock_groups-async-namemy_async_clks-groupwbClk-group

bftClkExample :Clock

ValidationValidatebothclocksaredefined

successfullyreport_clocksValidateinputjitterisdefined

successfullyreport_property[get_clocks

wbClk]get_propertyINPUT_JITTER[get_clocks

wbClk]Example :Clock

ValidationValidateclockuncertaintyisdefined

successfullyreport_timing-from[get_clockswbClk]-to[get_clocks

wbClk]Example :Clock

ValidationValidatebothclocksare

asynchronousreport_clock_interactionLauren

GaoDefiningClockGroupsSynchronousTwoclockshaveafixedphase

relationshipTheysharecommoncircuitry(common

node)Theysharethesameprimaryclock(sameinitial

phase)AsynchronousTwoclocksdonothaveafixedphase

relationshipTheydonotshareanycommoncircuitryinthedesignanddonothaveacommonprimary

clockTheydonothaveacommonperiodwithin1000cycles(unexpandable)andthetimingenginecannotproperlytimethem

togetherExclusiveTwoclockspropagateonasameclocktreeandreachthesamesequentialcellclockpinsbutcannotphysicallybeactiveatthesame

timeLogically

exclusiveTwoclocksaredefinedondifferentsource

rootsPhysically

exclusiveTwoclocksaredefinedonthesamesourcerootby"create_clock

-add"Clock

InteractionsClockInteractions

ExamplesMMCMclk0clk1clk2OSC1SynchronousMMCMclkaclkbclkcOSC2AsynchronousclktclkvBUFGMUXLogicExclusiveset_clock_groups[-namearg]

[-logically_exclusive][-physically_exclusive][-asynchronous][-groupargs][-quiet][-verbose]Useset_clock_groupstocreateclockexception

constraintset_clock_groups

–asynchronousset_clock_groups

–logically_exclusiveset_clock_groups

–physically_exclusiveClockGroupConstraint

TypesUseset_clock_groups–asynchronoustoefficientlyconstrain

suchclocksAsynchronousClock

Groupscreate_clock–nameCLKA–period10.0[get_portsCLKA]create_clock–nameCLKB–period5.0[get_portsCLKB]set_clock_groups–async–groupCLKA–group

CLKBset_false_path–from[get_clocksCLKA]–to[get_clocksCLKB]set_false_path–from[get_clocksCLKB]–to[get_clocks

CLKA]CLKA,CLKBcanbe

fromdifferent

portsOrdifferent

MMCMAsynchronousClock

GroupsMMCMclk0clk1clk2CLKAMMCMclkaclkbclkcCLKBPrimaryClocksAutoGeneratedClocksAsync

Clockscreate_clock–nameCLKA–period10.0[get_portsCLKA]create_clock–nameCLKB–period5.0[get_portsCLKB]set_clock_groups–async

\-group[get_clocks–include_generated_clocksCLKA]

\-group[get_clocks–include_generated_clocks

CLKB]BEWARE:

Thisoverridesanyset_max_delayconstraints!Example:Theclocksclk50andclk100aresynchronoustoeach

otherTheclocksclk33andclk66aresynchronoustoeach

otherTheclocksclk50andclk100areasynchronoustotheclocksclk33

andclk66Theconstraintfortheclockgroupswould

be:AsynchronousClock

Groupsset_clock_groups–async

\–group{clk50clk100}-group{clk33

clk66}Inthebelow

figureTheclocksCLK1andDIV_CLK1aresynchronoustoeach

otherTheclocksCLK1andDIV_CLK1areasynchronousto

CLKBAsynchronousClock

Groupscreate_generated_clock-nameDIV_CLK1–source\[get_pinsREGA1/C]-divide_by2[get_pins

REGA1/Q]set_clock_groups–async–group{CLK1DIV_CLK1}–group

{CLKB}REGA1SolutionGuidelineLogicallyexclusiveclocksshouldn’tinteractoutsidethe

MUXLogicallyexclusiveclocksaredefinedondifferentsource

rootsLogicallyExclusiveClock

GroupsCaseinwhichthepathsA,B,andCdonot

existLogicallyExclusiveClock

Groupsset_clock_groups–logically_exclusive-groupclk0–group

clk1CaseinwhichonlythepathsAorBorCexistLogicallyExclusiveClock

Groupscreate_generated_clock-nameclk0mux-divide_by1

\-source[get_pinsmux/I0][get_pinsmux/O]create_generated_clock-nameclk1mux-divide_by1

\-add-master_clockclk1-source[get_pinsmux/I1][get_pins

mux/O]set_clock_groups-physically_exclusive\-groupclk0mux-group

clk1muxGuidelinePhysicallyclockscannotphysicallyexistatthesame

timePhysicallyclocksaredefinedonthesamesource

rootPhysicallyExclusiveClock

GroupsTheFPGAyouareimplementingmustgoontwodifferentversionsofPCBboards.ToeasetheFPGAversionmanagement,therequirementistohaveasinglebitfileforbothboards.TheonlydifferencebetweentheboardsisthatthewbClkhasadifferentfrequencydependingontheconfiguration:ConfigurationA:wbClkisa100MHz

clockbftClkisa200MHz

clockAllCDCsbetweentheseclockdomainscanbetreatedas

asynchronousConfigurationB:wbClkisa150MHz

clockbftClkisa200MHz

clockAllCDCsbetweentheseclockdomainscanbetreatedas

asynchronousPhysicallyExclusiveClock

GroupsSolutionscreate_clock-namewbClk_A-period10.0[get_portswbClk]create_clock-namewbClk_B-period6.667[get_portswbClk]-addcreate_clock-namebftClk-period5.0[get_portsbftClk]set_clock_groups-physically_exclusive-nametwo_clk_grps

\-groupwbClk_A-groupwbClk_Bset_clock_groups-async-namemy_async_clks

\-group[get_clocks“wbClk_AwbClk_B”]-groupbftClkSayyouhave10clocksinyourdesign(clk1,clk2,…,

clk10)–Letusassumethatclocksclk1,clk2andclk3aresynchronousandyoucreatethefollowing

constraint–set_clock_groups–async–group{clk1clk2

clk3}Theclocksclk1,clk2andclk3aresynchronouswitheachotherbut

areasynchronoustoallotherclocksinthe

designTheotherclocks(clocksclk4,clk5…)areanalyzedassynchronoustoeach

otherTheaboveconstraintisthesame

as–set_clock_groups–async–group{clk1clk2clk3}–group

{clk4clk5...clk10}Usergeneratedclocksarenotautomaticallygroupedinthesamegroupasthe

master!–Intheaboveexampleifclk1_genisausergeneratedclockofclk1theyyou'd

needtoaddtheclk1_gentothesamegroupas

clk1–set_clock_groups-async-group{clk1clk1_genclk2

clk3}ThingstoKeepin

Mind…Lauren

GaoManageIP

ConstraintsAnIPcandeliveranumberofXDC

files<IP_Name>.xdcClockcreationcommandsaswellasallcommandswithoutoutsideclockdependencies<IP_Name>_clocks.xdcAllcommandswithdependenciestooutside

clocks<IP_Name>_ooc.xdcDefaulttoplevelclockdefinitions.UsedduringcreationofSynthesizedDesignCheckpoint

(DCP)<IP_Name>_board.xdcBoardSpecificphysical

constraintsPossiblyadditionalXDCfilesforsynthesisorimplementation

onlyXDCFilesGeneratedBy

IPConstraintFileProcessing

OrderIP_Name.xdcUser.xdcIP_Name_clocks.xdcBydefault,theVivadoIDEprocessesthecoreXDCfiles

<IP_Name.xdc>beforeanyuser

constraintsBydefault,theVivadoIDEprocessesthe<IP_Name>_clocks.xdcfileafteruserconstraintsandotherIPcoreXDC

files<IP_Name>_ooc.xdcisonlyusedintheDCPcreationwhenusingtherecommendeddefaultflow(IPsynthesizedOOCtothetop-level

design)report_compile_order

-constraintsConstraintsCreatedforIPDuring

Flowdout_touch.xdcUsedduringthecreationoftheSynthesisDesignCheckpoint

(.DCP)Containscommandstosetdont_touchpropertiesontheIP

topPreventstheinterfaceportsfrombeing

removedWillseethisbeingreadintheLogfortheIPdesign

RunConstraintsCreatedforIPDuring

Flow<IP

Name>_in_context.xdcThisfileiscreatedandstoredintheIPDCPfile,inthefollowing

conditions:TheIPoutputany

clocksTheIPhasaninstanceofI/O

buffersItisprocessedbeforetheend-user

constraintsItisnotnecessaryduringimplementationbecausetheIParenolongerablackboxWillseethisbeingreadintheglobalsynthesislog

fileDemoLauren

GaoUsingDesignRuleChecksin

VivadoAlwaysrunDRCearlyinthe

flowRunDRCaftereachmajordesign

stepAfter

ElaborateAfter

SynthesisAfter

ImplementationFixCriticalWarningsandErrorsbeforeproceedingtonext

stepDRC

MethodologyRule

DecksElaboratedDesignSynthesizedDesignImplementedDesignInvokingMethodology

CheckDesign

Stagesmethodology_checkstiming_checksRTLXDCElaborated

Design√√Synthesized

Design√√Implemented

Design√√Tcl:report_drcDEMOAlwaysrunDRCearlyinthe

flowRunDRCaftereachmajordesign

stepFixCriticalWarningsandErrorsbeforeproceedingtonext

stepSummaryLauren

GaoUnderstandingImplementation

StrategiesImplementationopt_designpower_opt_designplace_designpower_opt_designphys_opt_designroute_designphys_opt_designRetargetingExample:AMUXF7replacedbyaLUT3canbecombinedwithother

LUTsExample:Simplecellssuchasinvertersareabsorbedintodownstream

logicConstant

PropagationEliminated

logicExample:anANDwithaconstant0

inputReduced

logicExample:A3-inputANDwithaconstant1inputisreducedtoa2-input

ANDRedundant

logicExample:A2-inputORwithalogic0inputisreducedtoa

wireSweepRemovescellsthathaveno

loadsBlockRAMPower

OptimizationChangingtheWRITE_MODEonunreadportsoftruedual-portRAMsto

NO_CHANGEApplyingintelligentclockgatingtoblockRAM

outputsLogicOptimization

(opt_design)RemapRemapcombinesmultipleLUTsintoasingleLUTtoreducethedepthofthe

logicResynth

AreaResynthAreaperformsre-synthesisinareamodetoreducethenumberof

LUTs.ResynthSequential

AreaResynthSequentialAreaperformsre-synthesistoreducebothcombinationalandsequential

logicLogicOptimization

(opt_design)opt_designopt_design-directive

NoBramPowerOptopt_design-retarget-propconst

-sweepopt_design[-retarget][-propconst][-sweep][-bram_power_opt][-remap][-resynth_area][-resynth_seq_area][-directive

<arg>][-quiet]

[-verbose]Optimizedynamicpowerusingclockgatingbutdonotchange

theclocksorlogicofthe

designItcanberunAFTERLOGICOPTIMIZATIONorafter

placementPower

Optimizationpower_opt_designpower_opt_design[-quiet]

[-verbose]set_power_opt[-include_cells<args>][-exclude_cells

<args>][-clocks<args>][-cell_types<args>][-quiet]

[-verbose]set_power_opt-cell_types{bramreg}power_opt_designPlaceDesign

(place_design)PlaceDesign

DirectivesWLDrivenBlockPlacementAltWLDrivenPlacement(UltraScaleOnly)LateBlockPlacementExtraNetDelay_highExtraNetDelay_mediumExtraNetDelay_lowSpreadLogic_highSpreadLogic_mediumSpreadLogic_lowSSI_ExtraTimingOptSSI_SpreadSLLsSSI_BalanceSLLsSSI_BalanceSLRsSSI_HighUtilSLRsWire

LengthExtraNet

DelaySpread

LogicSSIplace_designplace_design[-directive<arg>][-no_timing_driven][-timing_summary][-unplace][-post_place_opt][-quiet]

[-verbose]-unplace:Unplacealltheinstanceswhicharenotlockedby

constraints-post_place_optRunoptimizationafterplacementtoimprovecriticalpathtimingattheexpenseofadditionalplacementandrouting

runtimeThisoptimizationcanberunatanystageafterplacement,andcan

beparticularlyeffectiveonarouted

designAnyplacementchangeswillresultinunroutedconnections,soroute_designwillneedtoberunafter

-post_place_optplace_designprocrunPPO{{numIters1}{enablePhysOpt1}}

{for{seti0}{$i<$numIters}{incri}

{place_design-post_place_optif{$enablePhysOpt!=0}

{phys_opt_design}route_designif{[get_propertySLACK[get_timing_paths]]>=0}

{break};#stopiftimingis

met}}place_designphys_opt_designroute_designrunPPO4

1PhysicalOptimization

(phys_opt_design)Physicaloptimizationperformstiming-drivenoptimizationon

thenegative-slackpathsofa

designTwomodesof

operationpost-placepost-routephys_opt_design[-fanout_opt][-placement_opt][-routing_opt][-rewire][-critical_cell_opt][-dsp_register_opt]

[-bram_register_opt][-bram_enable_opt][-shift_register_opt][-hold_fix]

[-retime][-force_replication_on_nets<args>][-directive<arg>][-critical_pin_opt][-clock_opt][-quiet]

[-verbose]RoutingRoutercanstartwithaplaceddesignthat

isUnroutedPartially

routedFully

routedroute_design[-unroute][-release_memory][-nets<args>][-physical_nets][-pin<arg>][-directive<arg>]

[-tns_cleanup][-no_timing_driven][-preserve][-delay][-auto_delay]-max_delay<arg>-min_delay<arg>[-timing_summary][-finalize][-quiet]

[-verbose]route_designroute_designwrite_checkpoint-force

$outputDir/post_routereport_timing_summary–file

\$outputDir/post_route_timing_summary.rpt#Getthenetsinthetop10criticalpaths,assignto

$preRoutessetpreRoutes[get_nets-of[get_timing_paths-max_paths

10