超大規(guī)模集成電路2017年秋段成華老師第四次作業(yè)

實(shí)用文檔Shownbelowarebuffer-chaindesigns.(1)Calculatetheminimumdelayofachainofinvertersfortheoveralleffectivefan-outof64/1.(2)UsingHSPICEandTSMC0.18umCMOStechnologymodelwith1.8Vpowersupply,designacircuitsimulationschemetoverifythemwiththeircorrespondentparametersofN,f,andtp.γ=1F=64∴f=所以最佳反相器數(shù)目約為3通過仿真可以得到tphl=1.3568E-11tplh=1.7498E-11tp0=1.5533E-11(2)N=1時，tphl=5.2735E-10tplh=8.1605E-10tpd=6.7170E-10N=2時，tplh=2.2478E-10tphl=2.5567E-10tpd=2.4023E-10N=3時，tphl=2.0574E-10tplh=2.1781E-10tpd=2.1178E-10N=4時，tplh=2.1579E-10tphl=2.2189E-10tpd=2.1884E-10從仿真結(jié)果可以看出N=3或者N=4時延遲時間最優(yōu)，且N=2、3、4得到的仿真延遲時間與理論推導(dǎo)的時間比較接近，比例基本上是18、15、15.3，而N=1時仿真得到的延遲時間遠(yuǎn)小于理論推導(dǎo)的時間，但是最優(yōu)結(jié)果依舊是N=3,f=4,tp=15。*SPICEINPUTFILE:Bsim3demo1.sp--achainofinverters.paramSupply=1.8.lib 'C:\synopsys\Hspice_A-2007.09\tsmc018\mm018.l'TT.optioncaptab.optionlistnodepostmeasout.tran10p6000p************************************************************.paramtdval=10p.meastrantplhtrigv(in)val=0.9td=tdvalrise=2+targv(out)val=0.9rise=2.meastrantphltrigv(in)val=0.9td=tdvalfall=2+targv(out)val=0.9fall=2.meastpdparam='(tphl+tplh)/2'*macrodefinitions**************************************************************nmos1*.subcktnmos1n1n2n3mnn1n2n3Gndnchl=0.2uw=0.4uad=0.2p^2pd=0.4uas=0.2p^2ps=0.4u.endsnmos1**pmos1*.subcktpmos1p1p2p3mpp1p2p3Vccpchl=0.2uw=0.8uad=0.4p^2pd=0.8uas=0.4p^2ps=0.8u.endspmos1*.subcktinv1inoutxmnoutinGndnmos1xmpoutinVccpmos1vccVccGndSupply.endsinv1**nmos2*.subcktnmos2n1n2n3mnn1n2n3Gndnchl=0.2uw=1.12uad=0.56p^2pd=1.12uas=0.56p^2ps=1.12u.endsnmos2**pmos2*.subcktpmos2p1p2p3mpp1p2p3Vccpchl=0.2uw=2.24uad=1.12p^2pd=2.24uas=1.12p^2ps=2.24u.endspmos2*.subcktinv2inoutxmnoutinGndnmos2xmpoutinVccpmos2vccVccGndSupply.endsinv2**nmos3*.subcktnmos3n1n2n3mnn1n2n3Gndnchl=0.2uw=3.2uad=1.6p^2pd=3.2uas=1.6p^2ps=3.2u.endsnmos3**pmos3*.subcktpmos3p1p2p3mpp1p2p3Vccpchl=0.2uw=6.4uad=3.2p^2pd=6.4uas=3.2p^2ps=6.4u.endspmos3*.subcktinv3inoutxmnoutinGndnmos3xmpoutinVccpmos3vccVccGndSupply.endsinv3**nmos4*.subcktnmos4n1n2n3mnn1n2n3Gndnchl=0.2uw=9.04uad=4.52p^2pd=9.04uas=4.52p^2ps=9.04u.endsnmos4**pmos4*.subcktpmos4p1p2p3mpp1p2p3Vccpchl=0.2uw=18.08uad=9.04p^2pd=18.08uas=9.04p^2ps=18.08u.endspmos4*.subcktinv4inoutxmnoutinGndnmos4xmpoutinVccpmos4vccVccGndSupply.endsinv4*maincircuitnetlistxinv1inout1inv1xinv2out1out2inv2xinv3out2out3inv3xinv4out3outinv4cloutGnd154.24fVininGnd0.9pulse(0.01.8219p40p40p1100p2400p).printtranv(in)v(out).endConsiderthelogicnetworkbelow,whichmayrepresentthecriticalpathofamorecomplexlogicblock.Theoutputofthe。networkisloadedwithacapacitancewhichis5timeslargerthantheinputcapacitanceofthefirstgate,whichisaminimum-sizedinverter.TheeffectivefanoutofthepathhenceequalsF=CL/Cg1=5.UsingHSPICEandTSMC0.18umCMOStechnologymodelwith1.8Vpowersupply,designacircuitsimulationschemetoverify(1)theOPTIMAZATIOMparametersofg,f,andsforeachoftheinverterandgatesandThepathlogicaleffortG=1*ThetotalpatheffortH=GFB=Theoptimalgateefforth=f1g1=f2g2=f3g3=f4g4=1.93g1=1g2=f1=1.93f2=1.16f3=1.16f4=1.93s1=1s2=1.16s3=1.34s4=2.6在所有的nmos和pmos均采用最小尺寸晶體管的情況下tplh=1.9047E-10tphl=2.2742E-10tpd=2.0895E-10在所有所有的mos管尺寸均是前一個mos管尺寸的2倍的情況下tplh=1.8353E-10tphl=2.4356E-10tpd=2.1355E-10在參數(shù)最優(yōu)的情況下tplh=1.7151E-10tphl=2.2853E-10tpd=2.0002E-10所以最優(yōu)參數(shù)為上面的推到過程。*SPICEINPUTFILE:Bsim3demo1.sp--achainofinverters.paramSupply=1.8.lib 'C:\synopsys\Hspice_A-2007.09\tsmc018\mm018.l'TT.optioncaptab.optionlistnodepostmeasout.tran10p6000p************************************************************.paramtdval=10p.meastrantplhtrigv(in)val=0.9td=tdvalrise=2+targv(out)val=0.9rise=2.meastrantphltrigv(in)val=0.9td=tdvalfall=2+targv(out)val=0.9fall=2.meastpdparam='(tphl+tplh)/2'*macrodefinitions**************************************************************nmos1*.subcktnmos1n1n2n3mnn1n2n3Gndnchl=0.2uw=0.4uad=0.2p^2pd=0.4uas=0.2p^2ps=0.4u.endsnmos1**pmos1*.subcktpmos1p1p2p3mpp1p2p3Vccpchl=0.2uw=0.8uad=0.4p^2pd=0.8uas=0.4p^2ps=0.8u.endspmos1*.subcktinv1inoutxmnoutinGndnmos1xmpoutinVccpmos1vccVccGndSupply.endsinv1**nmos2*.subcktnmos2n1n2n3n4mnn1n2n3n4nchl=0.2uw=0.772uad=0.386p^2pd=0.772uas=0.386p^2ps=0.772u.endsnmos2**pmos2*.subcktpmos2p1p2p3p4mpp1p2p3p4pchl=0.2uw=1.544uad=0.772p^2pd=1.544uas=0.772p^2ps=1.544u.endspmos2*.subcktnandin1in2in3outxmn1d1in1GndGndnmos2xmn2d2in2d1d1nmos2xmn3outin3d2d2nmos2xmp1outin1VccVccpmos2xmp2outin2VccVccpmos2xmp3outin3VccVccpmos2vccVccGndSupply.endsnand**nmos3*.subcktnmos3n1n2n3n4mnn1n2n3n4nchl=0.2uw=0.9uad=0.45p^2pd=0.9uas=0.45p^2ps=0.9u.endsnmos3**pmos3*.subcktpmos3p1p2p3p4mpp1p2p3p4pchl=0.2uw=1.79uad=0.895p^2pd=1.79uas=0.895p^2ps=1.79u.endspmos3*.subcktnorin1in2outxmn1outin1GndGndnmos3xmn2outin2GndGndnmos3xmp1outin1d1d1pmos3xmp2d1in2VccVccpmos3vccVccGndSupply.endsnor**nmos4*.subcktnmos4n1n2n3mnn1n2n3Gndnchl=0.2uw=1.044uad=0.522p^2pd=1.044uas=0.522p^2ps=1.044u.endsnmos4**pmos4*.subcktpmos4p1p2p3mpp1p2p3Vccpchl=0.2uw=2.0764uad=1.0382p^2pd=2.0764uas=1.0382p^2ps=2.0764u.endspmos4*.subcktinv2inoutxmnoutinGndnmos4xmpoutinVccpmos4vccVccGndSupply.endsinv2*maincircuitnetlistxinv1inout1inv1xnandout1VccVccout2nandxnorout2Gndout3norxinv2out3outinv2cloutGnd12.05fvccVccGndSupplyVininGnd0.9pulse(0.01.8219p40p40p1100p2400p).printtranv(in)v(out).end(2)theminimumdelayofthechain.在參數(shù)最優(yōu)的情況下tplh=1.7151E-10tphl=2.2853E-10tpd=2.0002E-10Shownbelowisalevelrestorecircuitofpasstransistor.(1)Withouttrans3istorMr,4verifybyusingHSPICEandTSMC0.18umCMOStechnologymodelwith1.8Vpowersupplythatthehighinputtothesignal-restoringinverteronlychargesuptoVDD-VTn.通過仿真，我們得到V(x)=1.38V，VTn=0.445V，所以Vx(2)AfterinsertingMr,verifythatthehighinputtothesignal-restoringinvertercanchargeuptoVDD.通過仿真得到V*SPICEINPUTFILE:Bsim3demo1.sp--achainofinverters.paramSupply=1.8.lib 'C:\synopsys\Hspice_A-2007.09\tsmc018\mm018.l'TT.optioncaptab.optionlistnodepostmeasout.tran10p6000p************************************************************.paramtdval=10p.meastrantphltrigv(in)val=0.9td=tdvalrise=2+targv(out)val=0.9fall=2.meastrantplhtrigv(in)val=0.9td=tdvalfall=2+targv(out)val=0.9rise=2.meastpdparam='(tphl+tplh)/2'.meastranvmaxmaxv(x)