EDA實驗(整理版)

1、數(shù)據(jù)選擇器MUX41A四選一library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mux41a isport(EN,A1,A0,D3,D2,D1,D0:in std_logic;Y:out std_logic);end mux41a;architecture one of mux41a issignal A:std_logic_vector(2 downto 0);beginA<=EN&A1&A0;Y<=D0 WHEN A="000"else

2、D1 WHEN A="001"ELSED2 WHEN A="010"ELSED3;END ONE;MUX61A六選一library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mux61a isport(D0,D1,D2,D3,D4,D5:in std_logic;A:std_logic_vector(2 downto 0);Y:out std_logic);end mux61a;architecture AA of mux61a isbeginY<

3、=D0 WHEN A="000" ELSED1 WHEN A="001" ELSED2 WHEN A="010" ELSED3 WHEN A="011" ELSED4 WHEN A="100" ELSED5 WHEN A="101" ELSE'Z'end AA;MUX441A四位四選一library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mux441a i

4、sport(A:in std_logic_vector(2 downto 0);D3,D2,D1,D0:in std_logic_vector(3 downto 0);Y:out std_logic_vector(3 downto 0);end mux441a;ARCHITECTURE ONE OF MUX441A ISBEGINY<=D0 WHEN A="000"ELSED1 WHEN A="001"ELSED2 WHEN A="010"ELSED3;END ONE; 譯碼器DEC38A 3-8譯碼器library ieee;

5、use ieee.std_logic_1164.all;entity DEC38A isport( A2,A1,A0:in std_logic; S1,S2,S3:in std_logic; Y:out std_logic_vector(7 downto 0);end entity DEC38A;architecture one of DEC38A issignal S:std_logic_vector(5 downto 0);beginS<=S1&S2&S3&A2&A1&A0;with S selectY<="11111110&q

6、uot; when "100000", "11111101" when "100001", "11111011" when "100010", "11110111" when "100011", "11101111" when "100100", "11011111" when "100101", "10111111" when "100110&q

7、uot;, "01111111" when "100111", "11111111" when others;end one;DEC_DISPLAY 共陰極數(shù)碼管library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity DEC_DISPLAY ISport(A:in std_logic_vector(3 downto 0);EN:IN STD_LOGIC;Ya,Yb,Yc,Yd,Ye,Yf,Yg:OUT STD_LOGIC);end

8、dec_display;architecture one of dec_display issignal s:std_logic_vector(4 downto 0);signal Y:std_logic_vector(6 downto 0);beginS<=EN&A;Ya<=Y(6);Yb<=Y(5);Yc<=Y(4);Yd<=Y(3);Ye<=Y(2);Yf<=Y(1);Yg<=Y(0);with s selectY<="1111110"when"10000", "0110000

9、"when"10001", "1101101"when"10010", "1111001"when"10011", "0110011"when"10100", "1011011"when"10101", "1011111"when"10110", "1110000"when"10111", "1111111"

10、when"11000", "1111011"when"11001", "1000000"when"11010", "0100000"when"11011", "0010000"when"11100", "0001000"when"11101", "0000100"when"11110", "0000010"when&q

11、uot;11111", "0000000"when others; end architecture one;ENC83A 8-3線普通二進制編碼器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity enc83a ISport(I7,I6,I5,I4,I3,I2,I1,I0:IN STD_LOGIC; Y2,Y1,Y0:OUT STD_LOGIC);END ENC83A; ARCHITECTURE ONE OF ENC83A IS SIGNAL S:STD_

12、LOGIC_VECTOR(7 DOWNTO 0); SIGNAL Y:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN s<=I7&I6&I5&I4&I3&I2&I1&I0; Y2<=Y(2); Y1<=Y(1); Y0<=Y(0); WITH S SELECT Y<="000" WHEN "11111110", "001" WHEN "11111101", "010" WHEN &quo

13、t;11111011", "011" WHEN "11110111", "100" WHEN "11101111", "101" WHEN "11011111", "110" WHEN "10111111", "111" WHEN "01111111", "000" WHEN OTHERS; END ARCHITECTURE; 觸發(fā)器DFF2A D觸發(fā)器library

14、 ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dff2a isport (CLK:in std_logic; D:in std_logic; RESET,SET:in std_logic; Q,QB:out std_logic);end entity dff2a;architecture one of dff2a issignal Q1:std_logic;begin po:process(CLK,RESET,SET)begin if(CLK'event and CLK='1&#

15、39;)then if(RESET='0') then Q1<='0' elsif(SET='0') then Q1<='1'else Q1<=D; end if;end if;end process;Q<=Q1;QB<=NOT Q1;end architecture one; JK1A JK觸發(fā)器LIBRARY IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity JK1A isport(SET,RESET,C

16、LK,J,K:IN STD_LOGIC;Q,QB:OUT STD_LOGIC);END JK1A;ARCHITECTURE ONE OF JK1A ISSIGNAL Q1:STD_LOGIC;SIGNAL S:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN PROCESS(CLK,RESET,SET,S)ISBEGINS<=J&K;IF(SET='0') THEN Q1<='1'ELSIF(RESET='0') THEN Q1<='0'ELSIF(CLK'EVENT AND

17、CLK='1')THENCASE S ISWHEN "00"=>Q1<=Q1;WHEN "10"=>Q1<='1'WHEN "01"=>Q1<='0'WHEN "11"=>Q1<=NOT Q1;WHEN OTHERS=>NULL;END CASE;END IF;END PROCESS;Q<=Q1;QB<=NOT Q1;END ARCHITECTURE ONE; 計數(shù)器CNT74161 74161芯片LI

18、BRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT74161 ISPORT(CLK,LDN,D3,D2,D1,D0,CLRN,ENT,ENP:IN STD_LOGIC; RCO,Q3,Q2,Q1,Q0:OUT STD_LOGIC); END CNT74161; ARCHITECTURE ONE OF CNT74161 IS SIGNAL D,Q: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL EN: STD_LOGIC_VECTOR(1 DOWNTO 0)

19、; BEGIND<=D3&D2&D1&D0;EN<=ENT&ENP;Q3<=Q(3);Q2<=Q(2);Q1<=Q(1);Q0<=Q(0);PROCESS(CLK,EN,LDN,CLRN,Q)BEGINIF(EN="11")THENIF(CLK'EVENT AND CLK='1')THENIF(LDN='0')THEN Q<=D;ELSE Q<=Q+1;END IF;end if;ELSIF(CLRN='0')THEN Q<=&quo

20、t;0000"ELSE Q<=Q;END IF;IF(Q="1111")THEN RCO <='1'ELSE RCO <='0'END IF;END PROCESS;END ARCHITECTURE ONE;CNT120 模120的7位二進制計數(shù)器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT120 ISPORT(clk:in std_logic;Q:OUT STD_LOGIC_VECTOR(6

21、DOWNTO 0);END CNT120;ARCHITECTURE ONE OF CNT120 IS SIGNAL Q1:STD_LOGIC_VECTOR(6 DOWNTO 0);BEGINPROCESS(CLK)BEGINIF CLK'EVENT AND CLK='1'THENIF(Q1=119)THEN Q1<="0000000"ELSE Q1<=Q1+1;END IF;end if;end process;Q<=Q1;end architecture one;BCD365 模365的BCD碼計數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity B