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1、Advanced Packaging TechOutline Package Development Trend 3D Package WLCSP & Flip Chip PackagePackage Development Trend SO Family QFP Family BGA FamilyPackage Development Trend CSP Family Memory Card SiP ModulePackage Development Trend3D Package3D Package3D Package IntroductionetCSP StackFunction

2、al IntegrationHighLowTape-SCSP (or LGA)S-CSP (or LGA)S-PBGAS-M2CSPStacked-SiP2 Chip StackWirebond2 Chip StackFlip Chip &WirebondMulti ChipStackPackage onPackage (PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP / S-QFP 3 S-CSPS-etCSPetCSP + S-CSP PS-fcCSP + SCSP PoP with interposerFS-CSP2FS-CS

3、P1Paper ThinPS-vfBGA + SCSPPiP 5SCSPSS-SCSP(paste)Ultra thin StackD2D3D4D2D2D3D4D2 PoP QFN4SS-SCSPStacked DieTop dieBottom dieFOW materilWireTSV TSV (Through Silicon Via)A through-silicon via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSV techn

4、ology is important in creating 3D packages and 3D integrated circuits. A 3D package (System in Package, Chip Stack MCM, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space. In most 3D packages, the stacked chips are wired together along their edge

5、s. This edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. In some new 3D packages, through-silicon via replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no

6、 added length or thickness. Wire Bonding Stacked DieTSV Whats PoP? PoP is Package on Package Top and bottom packages are tested separately by device manufacturer or subcon.PoPPoPPS-vfBGAPS-etCSPLow Loop WirePin Gate MoldPackage StackingWafer Thinning PoP Core TechnologyPoP Allows for warpage reducti

7、on by utilizing fully-molded structure More compatible with substrate thickness reduction Provides fine pitch top package interface with thru mold via Improved board level reliability Larger die size / package size ratio Compatible with flip chip, wire bond, or stacked die configurations Cost effect

8、ive compared to alternative next generation solutions Amkors TMV PoP Top viewBottom viewThrough Mold ViaPoP Ball Placement on top surface Ball Placement on bottom Die Bond Mold (Under Full optional) Laser drilling Singulation Final Visual InspectionBase MtlThermal effect Process Flow of TMV PoP Digi

9、tal(Btm die) + Analog(Middle die) + Memory(Top pkg) Potable Digital GadgetCellular Phone, Digital Still Camera, Potable Game UnitMemory dieAnalog dieDigital diespacerEpoxyPiPEasy system integrationFlexible memory configuration100% memory KGDThinner package than POPHigh IO interconnection than POPSma

10、ll footprint in CSP formatIt has standardball size and pitchConstructed with: Film Adhesive die attach Epoxy paste for Top PKG Au wire bonding for interconnection Mold encapsulation Why PiP?PiPMaterial for High Reliability Based on Low WarpageWafer ThinningFine Process Control Top Package Attach Die

11、 Attach etcOptimized Package DesignFlip ChipUnder-fillTop epoxyISM PiP Core TechnologyPiPMemory PKGSubstrateFlip chipMemory PKGFlip chipInner PKGAnalogAnalogSpacerDigitalInner PKGWB PIPFC PIPPiP PiP W/B PiP and FC PiPWLCSP & Flip Chip PackageWLCSP What is WLCSP?WLCSP(Wafer Level Chip Scale Packa

12、ging), is not same as traditional packaging method (dicing packaging testing, package size is at least 20% increased compared to die size). WLCSP is packaging and testing on wafer base, and dicing later. So the package size is exactly same as bare die size. WLCSP can make ultra small package size, a

13、nd high electrical performance because of the short interconnection.WLCSP Why WLCSP?Smallest package size: WLCSP have the smallest package size against die size. So it has widely use in mobile devices.High electrical performance: because of the short and thick trace routing in RDL, it gives high SI

14、and reduced IR drop.High thermal performance: since there is no plastic or ceramic molding cap, heat from die can easily spread out.Low cost: no need substrate, only one time testing. WLCSPs disadvantageBecause of the die size and pin pitch limitation, IO quantity is limited (usually less than 50pin

15、s).Because of the RDL, stagger IO is not allowed for WLCSP.RDL RDL: Redistribution Layer A redistribution layer (RDL) is a set of traces built up on a wafers active surface to re-route the bond pads. This is done to increase the spacing between each interconnection(bump). WLCSP Process Flow of WLCSP

16、WLCSP Process Flow of WLCSPFlip Chip PackageFCBGA(Passive Integrated Flip Chip BGA)(PI)-EHS-FCBGA(Passive Integrated Exposed Heat Sink Flip Chip BGA)(PI)-EHS2-FCBGA(Passive Integrated Exposed 2 pieces of Heat Sink Flip Chip BGA)MCM-FCBGA(Multi-Chip-Module FCBGA)PI-EHS-MP-FCBGA(Passive Integrated Exp

17、osed Heat Sink Multi Package Flip Chip)BumpBump DevelopmentBump DevelopmentBump DevelopmentC4 Flip Chip Whats C4 Flip Chip? C4 is: Controlled Collapsed Chip Connection Chip is connected to substrate by RDL and Bump Bump material type: solder, goldC4 Flip Chip BGA Main Features Ball Pitch:0.4mm - 1.2

18、7mm Package size: up to 55mmx55mm Substrate layer: 4-16 Layers Ball Count: up to 2912 Target Market: CPU、FPGA、Processor、 Chipset 、Memory、Router、 Switches、 and DSP etc. Main Benefits Reduced Signal Inductance Reduced Power/Ground Inductance Higher Signal Density Die Shrink & Reduced Package Footprint High Speed and High thermal supportC2 Flip Chip Wh