四位二進(jìn)制加法器實(shí)驗(yàn)

1、input Cin,output 3:0 SUM,output Cout);assign Cou匸SUM二A+B+Cin;Endmodule四、實(shí)驗(yàn)步驟與要求1 創(chuàng)建一個(gè)子目錄Lab2,并新建一個(gè)工程項(xiàng)目NeW PrqJeCt WizardCreate NeW PrOjectSPeCify PrOjeCt lOCatiOn and type.Ent r % name, lOCAtiOnSz Wd Conment for the projectN%m« :I%b21LOCati on sE s coding MyPxilinx 丄 ab lab2IOWorking Directory

2、：E:codingMy XilinX 丄 ab Iab21 ,Description :Select lhe type Of top-level SoTIrCe for the PrOjeCtTOP-leVel SOUrCe type ：HDL2 .建立一個(gè)Verilog HDL文件，將該文件添加到工程項(xiàng)目中并編譯整個(gè)項(xiàng)目，查看該電路所占用的邏輯單元(Logic Elements , LE)的數(shù)量3 對(duì)設(shè)計(jì)項(xiàng)目進(jìn)行時(shí)序仿真，記錄仿真波形圖測(cè)試代碼如下:module add4_tb;/ Inputs reg 3:0代 reg 3:0 B;reg Cin;/ Outputswire 3:0 Sum

3、;wire Cout;/ Instantiate the Unit Under Test (UUT) add4 uut (A(A),.Cin(Cin), Sum(Sum),.Cout(Cout)；initial begin/ Initialize Inputs A<=4,dO;B<=4,dO;Cin=l,bO;#1 $display("A B Cin SumCout=%b% b% b% b% b,A)B,Cin,Sunn)Cout); A<=4,dO;B<=4,dl;Cin=l,bO;#2 $display("A B Cin Su Cout=%b%

4、b% b%b% b：A,B,Cin,Sum,Cout); A<=4'dO;B<=4,d2;Cin=l,bO;#2 $display("A B Cin Su Cout=%b% b% b% b% b：ABCin,Sum,CoLit);A<=4'dO;B<=4,d3;Cin=l,bO;#2 $display("A B Cin Su Cout=%b% b% b%b% b：A,B,Cin,Sum,Cout); A<=4'dO;B<=4,d4;Cin=l,bO;#2 $display("A B Cin Su Cout

5、=%b% b% b%b% b：ABCin,Suiri,CoLit);A<=4,dl;B<=4,dO;Cin=l'bl;#2 $display("A B Cin Su Cout=%b% b% b% b% b：ABCin,Suiri,CoLit);A<=4'd2;B<=4,dO;Cin=l,bO;#1 $display("A B Cin SumCout=%b% b% b% b% b"AB,Cin,Sum,Cout);A<=4,d4;B<=4,dO;Cin=l,bl;#1 $display("A B Cin

6、Sum Cout=%b% b%b% b% bl,)A,B1Cin,Sum,Cout);end endmodule4 根據(jù)FPGA開(kāi)發(fā)板使用說(shuō)明書(shū)，對(duì)設(shè)計(jì)文件中的輸入、輸出信號(hào)分 配引腳。即使用開(kāi)發(fā)板上的波動(dòng)開(kāi)關(guān)代表電路的輸入，用發(fā)光二極管(LED)代表電路的輸出。引腳分布代碼：NET'AfO'1 LOC=nG3n;NET"A1" LOC二"F3：NET"A2" LOC二,E2"NET"A3U LOC=nN3M;NET"B0n LOC=,P11"NET,Bln LOC=nL3M;NET&qu

7、ot;B2n LOC=nK3M;NETnB3M L0C=,B4"NEFSumOr LOC=,N5"NET,SumlM LOC=MN4U;NETSum2r LOC=,P4U;NET,Sum3M LOC=,G1,'NET"Cin" LOC="A7U;NET"Cout" LOC=nP6M;5 重新編譯電路，并下載到FPGA器件中。改變撥動(dòng)開(kāi)關(guān)的位置，并觀察LED的亮、滅狀態(tài)，測(cè)試電路功能6 .根據(jù)實(shí)驗(yàn)流程和實(shí)驗(yàn)結(jié)果，寫(xiě)出實(shí)驗(yàn)總結(jié)報(bào)告，并對(duì)波形圖和實(shí)驗(yàn)現(xiàn)象進(jìn)行說(shuō)明。7 .完成實(shí)驗(yàn)后，關(guān)閉所有程序，并關(guān)閉計(jì)算機(jī)。實(shí)驗(yàn)現(xiàn)象：由波形圖可見(jiàn)，輸出由Cout, Sum組成，是A、B、低位進(jìn)位Cin的和，Cout是為和的進(jìn)位。用數(shù)據(jù)