數(shù)電研討醫(yī)用生產(chǎn)線設(shè)計報告._第1頁
數(shù)電研討醫(yī)用生產(chǎn)線設(shè)計報告._第2頁
數(shù)電研討醫(yī)用生產(chǎn)線設(shè)計報告._第3頁
數(shù)電研討醫(yī)用生產(chǎn)線設(shè)計報告._第4頁
數(shù)電研討醫(yī)用生產(chǎn)線設(shè)計報告._第5頁
已閱讀5頁,還剩12頁未讀, 繼續(xù)免費閱讀

下載本文檔

版權(quán)說明:本文檔由用戶提供并上傳,收益歸屬內(nèi)容提供方,若內(nèi)容存在侵權(quán),請進(jìn)行舉報或認(rèn)領(lǐng)

文檔簡介

1、PROJECT REPORT實驗課程:數(shù)字電路EDA實驗實驗名稱:醫(yī)用生產(chǎn)線【Requirement】ØBe able to preset the number of tablets per bottle,for example ,fifty tablets each bottle. Ø Every box contains twenty-four bottles, stop count until 18 Ø Use software to design the simulation,Quartus II will be better. 【Principle an

2、d framework given by teacher】【Our system framework】【1.0】【2.0】【Modular design and simulation】Keyboard prcessor【Function introduction】As project requirement, we can optional set keyboard size and what is the key arrangement. However , inconsideration of engineering application, we chose 4*4 keyboard ,

3、 as indicated below.Just as the picture illustrated above, We define “A” are the first counter enable pin .When the A pin is high ,corresponding counter accept 8-bit number as its period. So as B and C.D is the reset put which clear the number of register. *and # are use as back-up.Basic on this key

4、board framework we can easily achieve our program use VHDL.At first ,wedivide the keyboard into a 4 row and 4 column and then judge its value using case sentence.【Programming】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY KEYBOARD IS PORT(CLK: IN STD_LOGIC;ROW: IN STD_LOGIC_VECTOR(3 DOWNTO 0); /行向量

5、COL: IN STD_LOGIC_VECTOR(3 DOWNTO 0); /列向量DATA: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);F:OUT STD_LOGIC; /給寄存器判斷是否有輸入EN1: OUT STD_LOGIC;EN2: OUT STD_LOGIC;EN3: OUT STD_LOGIC);END ENTITY KEYBOARD;ARCHITECTURE RTL OF KEYBOARD ISSIGNAL MID: STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL NUM: STD_LOGIC_VECTOR(3 DOWNTO 0)

6、;BEGINPROCESS(CLK,ROW,COL)BEGINMID<=(ROW&COL);IF (CLK'EVENT AND CLK='1') THENCASE MID IS /使用的是4*4標(biāo)準(zhǔn)矩陣鍵盤WHEN "00010001"=> NUM<="0001"WHEN "00010010"=> NUM<="0010"WHEN "00010100"=> NUM<="0011"WHEN "00

7、100001"=> NUM<="0100"WHEN "00100010"=> NUM<="0101"WHEN "00100100"=> NUM<="0110"WHEN "01000001"=> NUM<="0111"WHEN "01000010"=> NUM<="1000"WHEN "01000100"=> NUM<

8、="1001"WHEN "10000010"=> NUM<="0000"WHEN "10001000"=> NUM<="1010"EN1<='0'EN2<='0'EN3<='0'/清零WHEN "00011000"=> NUM<="1111"EN1<='1'EN2<='0'EN3<='0'/

9、第一個計數(shù)器計數(shù)值WHEN "00101000"=> NUM<="1111"EN1<='0'EN2<='1'EN3<='0'/第二個計數(shù)器計數(shù)值WHEN "01001000"=> NUM<="1111"EN1<='0'EN2<='0'EN3<='1'/WHEN OTHERS=> NUM<="1111"/1111的時候表示數(shù)據(jù)無效E

10、ND CASE;END IF;DATA<=NUM;F<=(NUM(0) AND NUM(1) AND NUM(2) AND NUM(3);END PROCESS;END RTL;【Simulation waveform】Register【Function introduction】This register has 4-bit input and 8-bit output, and a input named “carry” is also add to this register . When carry equal to “1”, put the 4-bit input to

11、high output pin, when the other, the 4-bit input will be put into low output pin.【programming】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY REGISTER_DIY IS PORT(F: IN STD_LOGIC;CLK: IN STD_LOGIC;CARRY : IN STD_LOGIC;RIN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);OUT_LOW: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);OUT

12、_HIGH: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END REGISTER_DIY;ARCHITECTURE RTL OF REGISTER_DIY IS SIGNAL F_IN: STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN PROCESS(CLK,F,CARRY)BEGIN F_IN<=(F&CARRY);IF (R_IN=”1010”) THEN OUT_LOW=”0000”;OUT_HIGH=”0000”;ELSIF (CLK'EVENT AND CLK='1') THENCASE F_IN I

13、S WHEN "00"=> OUT_LOW<=RIN;WHEN "01"=> OUT_HIGH<=RIN;WHEN OTHERS=> NULL;END CASE;END IF;END PROCESS;END RTL;【Simulation waveform】BCD to binary convertorAt the very beginning, we should ask a question to ourselves. Why we need a BCD to binary converter?We use the ke

14、yboard to put in the number of pills per bottle which is from 0 to 99,it is BCD,but the counter only counts the binary number,so we need to convert the BCD to binary numbers.【Function introduction】At First, we divide the BCD into high bit and low bit, then use two registers to store them and convert

15、 high bit and low bit respectively. When we convert the high bit, we assume the low bit is zero, then convert the BCD with low bit zero to binary numbers. For example,0010(high bit) 00100000(BCD) 00010100(binary)Then we convert the low bit,similarly,we assume the high bit is zero, and then convert t

16、he BCD with high bit zero to binary numbers.For example,0010(low bit) 00000010(BCD) 00000010(binary)Finally,we need an adder to add the two binary numbers(high bit and low bit) to get the final binary numbers. Then we have finished BCD to binary conversion.00100010(BCD) 00010100(high bit)+00000010(l

17、ow bit) 00010110(binary number)【Programming】【BCD to binary (high-bit)】library IEEE;use IEEE.std_logic_1164.all; entityBCD_binary_high is port ( CLK : IN STD_LOGIC;BCD_high: in bit_vector(3 downto 0); binary_high:outbit_vector(7 downto 0); endBCD_binary_high; architecture RTL of BCD_binary_high is be

18、ginprocess(BCD_high,CLK) begin IF CLK'EVENT AND CLK='1' THEN caseBCD_high is when "0000" => binary_high<="00000000" when "0001" => binary_high<="00001010" when "0010" => binary_high<="00010100" when "0011&

19、quot; => binary_high<="00011110" when "0100" => binary_high<="00101000" when "0101" => binary_high<="00110010" when "0110" => binary_high<="00111100" when "0111" => binary_high<="010001

20、10"when "1000" => binary_high<="01010000" when "1001" => binary_high<="01011010"when others => binary_high<="00000001" (BCD high to binary)end case; END IF;end process; end RTL;【BCD to binary (low-bit)】library IEEE; use IEEE.st

21、d_logic_1164.all; entityBCD_binary_low is port ( BCD_low: in bit_vector(3 downto 0); binary_low:outbit_vector(7downto 0); endBCD_binary_low; architecture RTL of BCD_binary_low is begin process(BCD_low) begincaseBCD_low is when "0000" => binary_low<="00000000" when "000

22、1" => binary_low<="00000001" when "0010" => binary_low<="00000010" when "0011" => binary_low<="00000011"when "0100" => binary_low<="00000100"when "0101" => binary_low<="00000101&qu

23、ot;when "0110" => binary_low<="00000110" when "0111" => binary_low<="00000111" when "1000" => binary_low<="00001000" when "1001" => binary_low<="00001001" when others => binary_low<="01

24、000000" end case; end process; end RTL;【Simulation waveform】Figure 1 BCD to binary converter(high-bit)Figure 2BCD to binary converter(low-bit)Adder【Function introduction】we need an adder to add the two binary numbers(high bit and low bit) to get the final binary numbers. Then we have finished B

25、CD to binary conversion.【Programming】library IEEE; use IEEE.std_logic_1164.all; use; entityUnsigned_adder isport ( A,B: in std_logic_vector(7downto 0); S: out std_logic_vector (7downto 0); endUnsigned_adder ; architecture RTL of Unsigned_adder is beginS<=A + B; end RTL;【Simulation waveform】Simula

26、te successfully achieved the function of adder, but it has some delay and interference. I think it may caused by Race and Hazard.Counter【Function introduction】Set D and Q as the signalvariable .D resource from the key board .Q is the internal signal of counter ,it circulates upon D.Once D has been s

27、ettle ,Q is upcount for D times.When Q run for D times, Theres a OUTPUT pulse through Cd .One circulation end.【Programming】libraryieee; use ieee.std_logic_1164.all;use;entity bc3 isport(CLK:instd_logic; D:INstd_logic_vector(7 downto 0); Q:bufferstd_logic_vector(7 downto 0); Cd:outstd_logic;EN:instd_

28、logic);end; architecture ONE of bc3 is beginprocess(CLK) beginifCLK'event and CLK='1'and EN='0'then Q<=D;if Q<D-1 then Q<=Q+1;else Q<="00000000"end if;end if; end process;process(Q)beginif Q=D-1 then Cd<='1'else Cd<='0'end if;end proces

29、s;end;【Simulation waveform】assume EN is HIGH for 3 clock pulse .D is settle as 16.We can get the simulate wave form as below So the counters function has been realized.Counter for the sum of tablets【Function introduction】I use four Asynchronous decimal counter construct a big counter which count range

溫馨提示

  • 1. 本站所有資源如無特殊說明,都需要本地電腦安裝OFFICE2007和PDF閱讀器。圖紙軟件為CAD,CAXA,PROE,UG,SolidWorks等.壓縮文件請下載最新的WinRAR軟件解壓。
  • 2. 本站的文檔不包含任何第三方提供的附件圖紙等,如果需要附件,請聯(lián)系上傳者。文件的所有權(quán)益歸上傳用戶所有。
  • 3. 本站RAR壓縮包中若帶圖紙,網(wǎng)頁內(nèi)容里面會有圖紙預(yù)覽,若沒有圖紙預(yù)覽就沒有圖紙。
  • 4. 未經(jīng)權(quán)益所有人同意不得將文件中的內(nèi)容挪作商業(yè)或盈利用途。
  • 5. 人人文庫網(wǎng)僅提供信息存儲空間,僅對用戶上傳內(nèi)容的表現(xiàn)方式做保護(hù)處理,對用戶上傳分享的文檔內(nèi)容本身不做任何修改或編輯,并不能對任何下載內(nèi)容負(fù)責(zé)。
  • 6. 下載文件中如有侵權(quán)或不適當(dāng)內(nèi)容,請與我們聯(lián)系,我們立即糾正。
  • 7. 本站不保證下載資源的準(zhǔn)確性、安全性和完整性, 同時也不承擔(dān)用戶因使用這些下載資源對自己和他人造成任何形式的傷害或損失。

最新文檔

評論

0/150

提交評論