模數(shù)轉(zhuǎn)換器ADC應(yīng)用原理

1、AD0809應(yīng)用原理很全面的資料1. 0809的芯片說明：ADC0809是帶有8位A/D轉(zhuǎn)換器、8路多路開關(guān)以及微處理機(jī)兼容的控制邏輯的CMOS組件。它是逐次逼近式 A/D轉(zhuǎn)換器，可以和單片機(jī)直接接口。（1）ADC0809的內(nèi)部邏輯結(jié)構(gòu)由上圖可知，ADC0809由一個(gè)8路模擬開關(guān)、一個(gè)地址鎖存與譯碼器、一個(gè) A/D轉(zhuǎn) 換器和一個(gè)三態(tài)輸出鎖存器組成。 多路開關(guān)可選通8個(gè)模擬通道，允許8路模擬量分 時(shí)輸入，共用A/D轉(zhuǎn)換器進(jìn)行轉(zhuǎn)換。三態(tài)輸出鎖器用于鎖存 A/D轉(zhuǎn)換完的數(shù)字量，當(dāng) OE端為高電平時(shí)，才可以從三態(tài)輸出鎖存器取走轉(zhuǎn)換完的數(shù)據(jù)。（2）.引腳結(jié)構(gòu)IN0 IN7 : 8條模擬量輸入通道ADC0

2、809對(duì)輸入模擬量要求：信號(hào)單極性，電壓范圍是 0 5V，若信號(hào)太小，必 須進(jìn)行放大；輸入的模擬量在轉(zhuǎn)換過程中應(yīng)該保持不變，如若模擬量變化太快，則需 在輸入前增加采樣保持電路。地址輸入和控制線：4條ALE為地址鎖存允許輸入線，高電平有效。當(dāng) ALE線為高電平時(shí)，地址鎖存 與譯碼器將A，B，C三條地址線的地址信號(hào)進(jìn)行鎖存，經(jīng)譯碼后被選中的通道的模擬 量進(jìn)轉(zhuǎn)換器進(jìn)行轉(zhuǎn)換。A，B和C為地址輸入線，用于選通IN0 IN7上的一路模擬量 輸入。通道選擇表如下表所示。CBA選擇的 通道000IN0001IN10 10IN201|1IN3100IN4101IN5【110IN6【111IN7數(shù)字量輸出及控制線

3、：11條ST為轉(zhuǎn)換啟動(dòng)信號(hào)。當(dāng)ST上跳沿時(shí)，所有內(nèi)部寄存器清零；下跳沿時(shí)，開始進(jìn)行 A /D轉(zhuǎn)換；在轉(zhuǎn)換期間，ST應(yīng)保持低電平。EOC為轉(zhuǎn)換結(jié)束信號(hào)。當(dāng)EOC為高電平 時(shí)，表明轉(zhuǎn)換結(jié)束；否則，表明正在進(jìn)行 A/D轉(zhuǎn)換。0E為輸出允許信號(hào)，用于控制 三條輸出鎖存器向單片機(jī)輸出轉(zhuǎn)換得到的數(shù)據(jù)。0E = 1，輸出轉(zhuǎn)換得到的數(shù)據(jù)；0E=0,輸出數(shù)據(jù)線呈高阻狀態(tài)。D7 D0為數(shù)字量輸出線。CLK為時(shí)鐘輸入信號(hào)線。因ADC0809的內(nèi)部沒有時(shí)鐘電路，所需時(shí)鐘信號(hào)必須由外 界提供，通常使用頻率為500KHZ，VREF ( + ), VREF ()為參考電壓輸入。2. ADC0809應(yīng)用說明(1) .ADC0

4、809內(nèi)部帶有輸出鎖存器，可以與 AT89S51單片機(jī)直接相連。(2) .初始化時(shí)，使ST和OE信號(hào)全為低電平。(3) .送要轉(zhuǎn)換的哪一通道的地址到 A，B，C端口上。(4) .在ST端給出一個(gè)至少有100ns寬的正脈沖信號(hào)。(5) .是否轉(zhuǎn)換完畢，我們根據(jù)EOC信號(hào)來判斷。(6) .當(dāng)EOC變?yōu)楦唠娖綍r(shí)，這時(shí)給 OE為高電平，轉(zhuǎn)換的數(shù)據(jù)就輸出給單片機(jī) 了。3. 實(shí)驗(yàn)任務(wù)如下圖所示，從ADC0809的通道IN3輸入0 5V之間的模擬量，通過 ADC0809轉(zhuǎn) 換成數(shù)字量在數(shù)碼管上以十進(jìn)制形成顯示出來。ADC0809的VREF接+ 5V電壓。4. 電路原理圖5. 程序設(shè)計(jì)：(1) .進(jìn)行A/D轉(zhuǎn)

5、換時(shí)，采用查詢EOC的標(biāo)志信號(hào)來檢測(cè)A/D轉(zhuǎn)換是否完畢，若 完畢則把數(shù)據(jù)通過P0端口讀入，經(jīng)過數(shù)據(jù)處理之后在數(shù)碼管上顯示。(2) .進(jìn)行A/D轉(zhuǎn)換之前，要啟動(dòng)轉(zhuǎn)換的方法：ABC = 110選擇第三通道ST = 0，ST = 1，ST = 0產(chǎn)生啟動(dòng)轉(zhuǎn)換的正脈沖信號(hào).(3) .關(guān)于0809的計(jì)算：ad0809是根據(jù)逐位逼近的方法產(chǎn)生數(shù)據(jù)的。參考電壓為0-5V的話。以0809八位255的轉(zhuǎn)換精度每一位的電壓值為(5-0)/2550.0196V設(shè)輸入電壓為X則：X-27*0.0196>=0則AD7=1否則AD7=0。X-26*0.0196>=0則AD6=1否則AD6=0。X-20*0.0

6、196>=0則AD0=1否則AD0=0。(27指2的7次方。2620同理)若參考電壓為0-1V(1-0)/2550.0039V精度自然高了。可測(cè)量范圍小了。1) 匯編源程序：CH EQU 30HDPCNT EQU 31HDPBUFEQU33HGDATAEQU32HST BITP3.0OE BIT P3.1EOC BIT P3.2ORG OOHLJMP STARTORG OBHLJMP TOXORG 30HSTART: MOV CH,#0BCHMOV DPCNT,#00HMOV R1,#DPCNTMOV R7,#5MOV A,#10MOV R0,#DPBUFLOP: MOV R0,AINC

7、 R0DJNZ R7,LOPMOV R0,#00HINC R0MOV R0,#00HINC R0MOV R0,#00HMOV TMOD,#01HMOV TH0,#(65536-4000)/256MOV TL0,#(65536-4000) MOD 256SETB TR0SETB ET0SETB EAWT: CLR STSETB STCLR STWAIT: JNB EOC,WAITSETB OEMOV GDATA,P0CLR OEMOV A,GDATAMOV B,#100DIV ABMOV 33H,AMOV A,BMOV B,#10DIV ABMOV 34H,AMOV 35H,BSJMP WTT0

8、X: NOPMOV TH0,#(65536-4000)/256MOV TL0,#(65536-4000) MOD 256MOV DPTR,#DPCDMOV A,DPCNTADD A,#DPBUFMOV R0,AMOV A,R0MOVC A,A+DPTRMOV P1,AMOV DPTR,#DPBTMOV A,DPCNTMOVC A,A+DPTRMOV P2,AINC DPCNTMOV A,DPCNTCJNE A,#8,NEXTMOV DPCNT,#00HNEXT: RETIDPCD: DB 3FH,06H,5BH,4FH,66HDB 6DH,7DH,07H,7FH,6FH,00HDPBT: DB

9、 0FEH,0FDH,0FBH,0F7HDB 0EFH,0DFH,0BFH,07FHEND2) C語言源程序#i ncludeunsigned char code dispbitcode=0xfe,0xfd,0xfb,0xf7, 0xef,0xdf,0xbf,0x7f;unsigned char code dispcode=0x3f,0x06,0x5b,0x4f,0x66, 0x6d,0x7d,0x07,0x7f,0x6f,0x00;unsigned char dispbuf8=10,10,10,10,10,0,0,0;unsigned char dispcount;sbit ST="

10、;P3"A0;sbit 0E="P3W；sbit EOC="P3"A2;unsigned char channel="0xbc"/IN3 unsigned char getdata;void main (void)TMOD=0x01;TH0=(65536-4000)/256;TL0=(65536-4000)%256;TR0=1;ET0=1;EA=1;P3=cha nn el;while(1)ST=0;ST=1;ST=0;while(EOC=0);OE=1;getdata=P0;OE=0;dispbuf2=getdata/100; ge

11、tdata=getdata%10;dispbuf1=getdata/10;dispbuf0=getdata%10;void t0(void) interrupt 1 using 0TH0=(65536-4000)/256;TL0=(65536-4000)%256;P1=dispcodedispbufdispco un t;P2=dispbitcodedispco un t;dispco un t+;if(dispco un t=8)dispco un t=0;3) FPGA 實(shí)現(xiàn)的程序：(verilog )module AD0809(clk,/ 脈寬(至少 100 ns)rst_n,EOC,

12、約100us后EOC變?yōu)楦唠娖睫D(zhuǎn)換結(jié)束START, 啟動(dòng)信號(hào)，上升沿有效(至少100 ns)OE,高電平打開三態(tài)緩沖器輸出轉(zhuǎn)換數(shù)據(jù)ALE, 高電平有效，選擇信道口ADDA,/因?yàn)锳DDB,ADDC都接地了，這里只有ADDA為變量 DATA,/ 轉(zhuǎn)換數(shù)據(jù)DATA_R);output START,OE,ALE,ADDA;in putEOC,clk,rst_n;in put7:0DATA;output7:0 DATA_R;regSTART,OE,ALE,ADDA;reg7:0 DATA_R;reg4:0 CS,NS;parameter IDLE=5”b00001,START_H=5”b00010,S

13、TART_L=5”b00100, CHECK_END=5''b01000,GET_DATA=5''b10000;always (*)case(CS)IDLE:NS=START_H;START_H:NS=START_L;START_L:NS=CHECK_END;CHECK_END:if(EOC)NS=GET_DATA; elseNS=CHECK_END; GET_DATA:NS=IDLE;default:NS=IDLE;endcasealways (posedge clk)if(!rst_n)CS<=IDLE; elseCS<=NS;always (p

14、osedge clk)case(NS)IDLE:begi nOE<=0;START<=0;ALE<=0;ADDA<=1;endSTART_H:begi nOE<=0;START<=1;產(chǎn)生啟動(dòng)信號(hào)ALEv=1;ADDA<=1; 選擇信道口 IN0endSTART_L:begi nOE<=0;START<=0;ALE<=1;啟動(dòng)信號(hào)脈寬要足夠長(zhǎng)，在啟動(dòng)的時(shí)候ALE要一直有效endCHECK_END:begi nOE<=0;START<=0;ALE<=0;endGET_DATA:begi nOE<=1;高電平打開三

15、態(tài)緩沖器輸出轉(zhuǎn)換數(shù)據(jù)DATA_Rv=DATA;提取轉(zhuǎn)換數(shù)據(jù)START<=0;ALE<=0;enddefault:begi nOE<=0;START<=0;ALE<=0;ADDA<=0;endendcaseen dmodule4) FPGA實(shí)現(xiàn)的程序：(VHDLLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY AD0809 ISPORT( D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK,EOC: IN STD_LO GI

16、C;CLOCK:IN STD_LOGIC;ALE,START,OE,LOCK0: OUT STD_LOGIC;DOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);END AD0809;ARCHITECTURE behav OF AD0809 ISTYPE states IS (st0,st1,st2,st3,st4);SIGNAL current_state,next_state:states:=st0;SIGNAL REGL :STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNA

17、L LOCK :STD_LOGIC;SIGNAL CNT1:STD_LOGIC_VECTOR(0 DOWNTO 0);SIGNAL A :INTEGER RANGE 0 TO 1;SIGNAL LOWDATA:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL HIGHDATA:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL LOWLED7S:STD_LOGIC_VECTOR(6 DOWNTO 0);SIGNAL HIGHLED7S:STD_LOGIC_VECTOR(6DOWNTO 0);BEGINLOCK0<=LOCK;PROCESS(REG

18、L)BEGINLOWDATA<=REGL(3 DOWNTO 0);HIGHDATA<=REGL(7 DOWNTO 4);CASE LOWDATA ISWHEN"0000"=>LOWLED7S<="0111111"WHEN"0001"=>LOWLED7S<="0000110"WHEN"0010"=>LOWLED7S<="1011011"WHEN"0011"=>LOWLED7S<="1001

19、111"WHEN"0100"=>LOWLED7S<="1100110"WHEN"0101"=>LOWLED7S<="1101101"WHEN"0110"=>LOWLED7S<="1111101"WHEN"0111"=>LOWLED7S<="0000111"WHEN"1000"=>LOWLED7S<="1111111"WHEN&q

20、uot;1001"=>LOWLED7S<="1101111"WHEN"1010"=>LOWLED7S<="1110111"WHEN"1011"=>LOWLED7S<="1111100"WHEN"1100"=>LOWLED7S<="0111001"WHEN"1101"=>LOWLED7S<="1011110"WHEN"1110"=

21、>LOWLED7S<="1111001"WHEN"1111"=>LOWLED7S<="1110001"WHENOTHERS=> Null;END CASE;CASE HIGHDATA ISWHEN"0000"=>HIGHLED7S<="0111111"WHEN"0001"=>HIGHLED7S<="0000110"WHEN"0010"=>HIGHLED7S<="

22、1011011"WHEN"0011"=>HIGHLED7S<="1001111"WHEN"0100"=>HIGHLED7S<="1100110"WHEN"0101"=>HIGHLED7S<="1101101"WHEN"0110"=>HIGHLED7S<="1111101"WHEN"0111"=>HIGHLED7S<="0000111&qu

23、ot;WHEN"1000"=>HIGHLED7S<="1111111"WHEN"1001"=>HIGHLED7S<="1101111"WHEN"1010"=>HIGHLED7S<="1110111"WHEN"1011"=>HIGHLED7S<="1111100"WHEN"1100"=>HIGHLED7S<="0111001"WHEN&qu

24、ot;1101"=>HIGHLED7S<="1011110"WHEN"1110"=>HIGHLED7S<="1111001"WHEN"1111"=>HIGHLED7S<="1110001"WHENOTHERS=> Null;END CASE;END PROCESS;PROCESS(CLOCK)BEGINIF CLOCK'EVENT AND CLOCK='1' THEN CNT1<=CNT1+1;END IF;END

25、 PROCESS;PROCESS(CNT1)BEGINCASE CNT1 ISWHEN "0" =>SEL<="111" A<=0;WHEN "1" =>SEL<="110" A<=1;WHEN OTHERS =>NULL;END CASE;END PROCESS;PROCESS(A)BEGINCASE A ISWHEN 0 =>DOUT<二LOWLED7S;WHEN 1 =>DOUT<二HIGHLED7S;WHEN OTHERS =>NULL;END CASE;END PROCESS;COM: PROCESS(curre nt_state,EOC)BEGINCASE current_state ISWHEN st0=>ALE<='0：STAR