數(shù)字系統(tǒng)設(shè)計(jì)與vhdl課件

1、數(shù)字系統(tǒng)設(shè)計(jì)第三講 同步時(shí)序設(shè)計(jì)2提綱記分板和控制器加法器全加器行波進(jìn)位加法器先行進(jìn)位加法器串行加法器記分板和控制器（Score board & controller輸入：遞增記分INC，遞減記分DEC，復(fù)位信號(hào)RESET輸出：兩個(gè)7段顯示器具體操作：當(dāng)遞增輸入為1，記分板上數(shù)字加1當(dāng)遞減輸入為1，記分板上數(shù)字減1當(dāng)INC和DEC同時(shí)為1，維持當(dāng)前狀態(tài)當(dāng)RESET為1并持續(xù)5個(gè)連續(xù)周期后，記分板上記分置02數(shù)字BCD計(jì)數(shù)器2 BCD-七段數(shù)碼管顯示譯碼器abcdfegabcdgfeINCDECRESET記分板和控制器（Score board & controllerBCD=0rstcnt=0T

2、F0001rstrstcnt=4rstcnt+inc=1dec=0BCD+rstcnt=0BCD-rstcnt=0inc=0dec=0rstcnt=0s0s1TTFinc=0dec=1FTFT數(shù)字BCD計(jì)數(shù)器的ASM記分板和控制器的RTL描述記分板和控制器的RTL描述記分板和控制器的RTL描述記分板和控制器的RTL描述全加器 full adderFull_AdderSUMBACOUTCIN全加器 full adderYXSUMCOUTCINentity Full_Adder isport (A, B,CIN: in BIT; SUM, COUT: out BIT);end Half_Adder

3、;architecture Full_Adder of Full_Adder isbeginSUM = A xor B xor CIN after 15ns;COUT = (A and B) or (B and CIN) or (CIN and A) after 10ns;end Full_Adder;若一個(gè)門delay為tg,Full adders delay？32位行波加法器ripple-carry adderRipple_AdderSBACOUT CINBASUMCOUTCINFull_AdderS(1)B(1)A(1)C(1)Full_AdderS(2)B(2)A(2)C(2)Full

4、_AdderS(31)B(31)A(31)COUTFull_AdderS(0)B(0)A(0)C(0)CINSCOUTCIN行波加法器延遲？如果RCA的一個(gè)門延遲為1ns，那么32位RCA的最大工作頻率是多少？32位行波加法器ripple-carry adderentity Ripple_Adder is port (A, B: in bit_vector(31 downto 0); CIN: in bit; S: out bit_vector(31 downto 0); COUT: out bit);end Ripple_Adder;architecture Ripple_Adder of

5、Ripple_Adder is component Full_Adder port(A,B,CIN: in bit; SUM, COUT: out bit); end component; signal C: bit_vector(32 downto 0);Begin C(0) = CIN; COUT = C(32); RC: for i in 31 downto 0 generate SI: Full_Adder port map (A(i), B(i), C (i), S(i), C(i+1); end generate;end Ripple_Adder;先行進(jìn)位加法器Carry look

6、-ahead adder一個(gè)流行的快速加法器這個(gè)電路能在同一時(shí)間計(jì)算進(jìn)位carry有2個(gè)函數(shù)：generate & propagate先行進(jìn)位加法器Carry look-ahead adderci+1 = ai bi + (ai xor bi) ciGi = ai biPi = ai + bi先行進(jìn)位加法器Carry look-ahead adder通過(guò)Pi和Gi計(jì)算SUM和CARRY:si = ai xor bi xor ci = ci xor Pici+1 = Gi + Pici反復(fù)使用上式得到:ci+1 = Gi + Pi(Gi-1 + Pi-1ci-1)ci+1 = Gi + PiGi

7、-1 + PiPi-1 (Gi-2 + Pi-1ci-2)4位先行進(jìn)位加法器Carry look-ahead adder可見(jiàn)任意級(jí)的進(jìn)位都可以直接計(jì)算，而無(wú)需等待進(jìn)位從前面的各個(gè)級(jí)逐級(jí)傳遞過(guò)來(lái)任意級(jí)的進(jìn)位可獨(dú)立運(yùn)算4位先行進(jìn)位加法器Carry look-ahead adder延遲？4位先行進(jìn)位加法器Carry look-ahead adderVHDL描述課本p15016位先行進(jìn)位加法器Carry look-ahead adder4位CLA全加器4位CLA全加器4位CLA全加器4位CLA全加器A1512 B1512A118 B118A74 B74A30 B30S G P CS G P CS G

8、P CS G P C先行進(jìn)位邏輯S3-0S7-4S11-8S15-12GG PPG3 P3 C3G2 P2 C2G1 P1 C1G0 P0C0PG=P3P2P1P0GG=G3+P3G2+P3P2G1+P3P2P1G0延遲？32位加法器的行為描述Library IEEE;Use IEEE.numeric_bit.all;Entity Adder32 is port(A,B: in unsigned (31 downto 0); Ci: in bit; - inputs S: out unsigned (31 downto 0); Co : out bit); - outputsEnd Adder

9、32;Architecture overload of Adder32 isSignal sum33: unsigned (32 downto 0);Begin Sum33 Ci); -Adder S = sum33(31 downto 0); Co O 1 0.694 0.436 a_0_IBUF (a_0_IBUF) LUT2:I0-O 1 0.086 0.000 Madd_s_lut (Madd_s_lut) MUXCY:S-O 1 0.305 0.000 Madd_s_cy (Madd_s_cy) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_c

10、y) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) (MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) XORCY:CI-O 1 0.300 0.235 Madd_s_xor (s_31_OBUF) OBUF:I