計(jì)算機(jī)組成與結(jié)構(gòu)：chapter7 Input Output

ComputerOrganization&ArchitectureChapter7

Input/OutputMotivationforInput/Output5ComponentsofAnyComputerMotivationforInput/OutputI/OishowhumansinteractwithcomputersI/Ogivescomputersacapabilityoflong-termmemory.I/Oletscomputersdoamazingthings:Readpressureofsynthetic

handand

controlsynthetic

armandhandoffiremanControlpropellers,fins,

communicateinBOB

(BreathableObservableBubble)ComputerwithoutI/OlikeacarwithoutwheelsMotivationforInput/OutputWidevarietyofperipheralsDeliveringdifferentamountsofdataAtdifferentspeedsAccordingtodifferenttimingsequenceIndifferentformatsAllslowerthanCPUandRAMPeripheralsdonotconnectdirectlytosystembusNeedI/OmodulesComputerMotivationforInput/OutputInput/OutputModuleInterfacetoCPUandMemoryInterfacetooneormoreperipheralsI/OmodulararchitectureisdesignedtoprovideasystematicmeansofcontrollinginteractionwithoutsideworldandprovidetheO.SwithinformationtomanageI/Oactivityeffectively7.1ExternalDevices

GenericModelofI/OModularHumanreadableScreen,printer,keyboardMachinereadableMonitoringandcontrolCommunicationModemNetworkInterfaceCard(NIC)I/ODeviceExamplesandSpeedsI/OSpeed:bytestransferredpersecond

(frommousetodisplay:1-to-million)

Device Behavior Partner DataRate

(KBytes/s)Keyboard Input Human 0.01Mouse Input Human 0.02Voiceoutput Output Human 5.00Floppydisk Storage Machine 50.00Laserprinter Output Human 100.00Magneticdisk Storage Machine 10,000.00Network-LAN IorO Machine 10,000.00Graphicsdisplay Output Human 30,000.00

ExternalDeviceBlockDiagramKeyboardandMonitorThemostcommonmeansofcomputer/useriskeyboardandmonitorKeyboardworkingprinciple(A/D)Akeyanelectronicsignalbitpattern(transducer)BitpatternI/OmodularProcessedandstoredasASCⅡincomputerMonitorworkingasoutput(D/A)OnthecontraryASCⅡASCⅡ:AmericanStandardCodeforInformationInterchangeAcharacterisrepresentedby7-bitbinarycode,total:128differentcharactersDEL:1111111=127A:1000001=65;a:1100001=971:0110001=49;OtherscanseeTable7.1ConverttoUppercasecisalowercaseletter;C=c-32;c&=0xdf;CExample

b:98=11000101100010&1101111101000010=66=BNote:nonreversibleDiskdriveContaintwotypesofelectronicsOnetypeforexchangingdata,controlandstatussignalswithanI/OmoduleTheotherforcontrollingthediskread/writemechanism7.2I/OModules

FunctionofI/OModuleControl&TimingCPU~I/OCommunicationDevice~I/OCommunicationMemory~I/OcommunicationDataBufferingErrorDetectionI/OStepsCPUchecksI/OmoduleanddevicestatusI/OmodulereturnsstatusIfready,CPUrequestsdatatransferI/OmodulegetsdatafromdeviceI/OmoduletransfersdatatoCPUProgrammed-I/OInterrupt-DrivenI/ODMA/ChannelI/OCommunicationCommanddecoding:

Readsector,Seektrack,ScanIDWhichblockscanbereadorwritten.DataexchangeExternaldataI/Omodulebufferthroughlocalbus

I/OmodulebufferCPU/memorythroughsystembus

StatusreportingBusy,ready,error,etcAddressrecognitionRecognizeeachperipheralDataBufferingAnimportantroleofI/OmodularAdaptperipheralstoCPUormainmemoryintheirvelocitiesCPU/DRAMI/ObufferI/ObufferperipheralsErrorDetectionAnI/OmodularisoftenresponsibleforerrordetectionandreportingerrorstoCPUOneclassoferrorsishardwarefailureMechanicalorelectricalE.g.:paperjam,baddisktrackAnotherclassoferrorsistransmittingerrorsBiterrorsDatalosses

I/OModuleStructureI/OModuleDecisionsSupportmultipleorsingledeviceHideorrevealdevicepropertiestoCPUControldevicefunctionsorleaveforCPUAlsoO/Sdecisionse.g.UnixtreatseverythingitcanasafileInputOutputModesProgrammedInterruptdrivenDirectMemoryAccess(DMA)I/OChannelI/Oprocessor7.3ProgrammedI/OWithprogrammedI/O,dataareexchangedbetweentheCPUandI/OmodularCPUhasdirectcontroloverI/OinaprogramSensingstatusRead/writecommandsTransferringdataCPUwaitsforI/OmoduletocompleteoperationwhenitissuesanI/OcommandWastesCPUtimeCPUencountersanI/OinstructionsItexecutesit,sendacommandtoI/Omodular,waitingfortheI/OmodularreadyI/OmodularperformsthecommandandthensettheappropriatebitintheI/OstatusregisterCPUperiodicallychecksthestatusbituntilitfindtheoperationcompletedI/OCommandsCPUissuesaddressIdentifiesmodule&device(if>1permodule)CPUissuescommands:4commandsControl-tellingmodulewhattodoe.g.rewind,opendiskdrive,etcTest-checkstatuse.g.power?Error?Read/WriteModuletransfersdataviabufferfrom/todeviceAddressingI/ODevicesUnderprogrammedI/Odatatransferisverylikememoryaccess(CPUviewpoint)EachdevicegivenuniqueidentifierCPUcommandscontainidentifier(address)I/OMappingMemorymappedI/ODevicesandmemoryshareanaddressspace0xxxxxx,1xxxxxxI/Olooksjustlikememoryread/writeNospecialcommandsforI/OLargeselectionofdevicesavailableIsolatedI/OSeparateaddressspacesNeedI/OormemoryselectlinesSpecialcommandsforI/OLimitedset

MemoryMappedandIsolatedI/OSummaryAdvantage:Simple:processoristotallyincontrolanddoesallDisadvantage:PollingoverheadcanconsumealotofCPUtimeSolution:useexceptionmechanismtohelpI/O.InterruptprogramwhenI/Oready,returnwhendonewithdatatransfer7.4InterruptDrivenI/OOvercomesCPUwaitingNorepeatedCPUcheckingofdeviceI/OmoduleinterruptswhenreadyInterruptDrivenI/OBasicOperationCPUissuesreadcommand,andthendootherthingsI/OmodulegetsdatafromperipheralwhilstCPUdoesotherworkI/OmoduleinterruptsCPUCPUrequestsdataI/OmoduletransfersdatathroughbusAtlast,CPUrecoverpreviousworkCPUViewpointIssuereadcommandDootherworkCheckforinterruptatendofeachinstructioncycleIfinterrupted:-Savecontext(registers)ProcessinterruptFetchdata&storeContinuepreviousworkI/OModuleViewpointReceiveaREADcommandfromCPUDetectthestateoftheperipheralReaddatafromtheperipheral,putitintoregistersSignalaninterrupttoCPUWaituntilitsdataarerequestedbyCPUPlacethedataonthedatabusReadingbasedoninterruptI/OSimpleinterruptprocessingChangesinMemoryandRegisters

foranInterruptDesignIssuesHowdoyouidentifythemoduleissuingtheinterrupt?Howdoyoudealwithmultipleinterrupts?i.e.aninterrupthandlerbeinginterruptedSolutionsMultipleinterruptlinesDifferentlineforeachmodule,LimitsnumberofdevicesSoftwarepollCPUaskseachmoduleinturnthroughinterrupt-servicesubroutineCommand+addressofI/OmoduleReadaddressablestatusregistercontainedineachI/OmoduleCPUbranchestothedeviceserviceroutineSlow(timeconsuming)

DaisychainorHardwarepollBus

AllI/OmodulesshareacommoninterruptrequestlineOnceCPUsensesaninterrupt,InterruptAcknowledgesentdownachainModuleresponsibleplacesvector(address,id)onbusCPUusesvectortopointtoanappropriatedevice-serviceroutineReferredtoasvectoredinterruptArbitration(vectored)ModulemustclaimthebusbeforeitcanraiseinterruptCPUdetectstheinterrupt,responditthroughinterruptacknowledgeline.I/Omoduleplacesvectoronthedatabuse.g.PCI&SCSIMultipleInterruptsProcessingWithmultiplelines,EachinterruptlinehasapriorityHigherprioritylinescaninterruptlowerprioritylinesWithsoftwarepolling,theorderinwhichmodulesarepolleddeterminestheirpriorityWithdaisy,theorderofmodulesonthedaisydeterminestheirpriorityExample—Intel82C59A82C59Aisachip,interruptcontroller,adaptivetoIntel80386CPU80386hasoneINTRpinandoneINTApinDevices82C59ACPUAsingle82C59Acanhandleupto8devices,formoredevices,cascadeisused(seefig.7.9,pp.214)82C59A’ssoleresponsibilityisthemanagementofinterrupt

Cascadeof82C59As

80x86INTR82C59AIRQ0IRQ1IRQ2IRQ3IRQ4IRQ5IRQ6IRQ782C59AIRQ0(8)IRQ1(9)IRQ2(10)IRQ3(11)IRQ4(12)IRQ5(13)IRQ6(14)IRQ7(15)(IRQ2)SequenceofEvents82C59Aacceptsinterruptsfromdevices82C59Adeterminesonewiththehighestpriority82C59Asignals80386(raisesINTRline)CPUAcknowledges(INTA)82C59AputscorrectvectorondatabusCPUprocessesinterrupt,communicatewithI/Omodule82C59Aisprogrammable:bysettingthecontrolwordinthe82C59A,CPUmaydeterminethedevices’priorityFullynestedTheinterruptrequestsareorderedinpriorityfromIR0toIR7,allchipsaresameasthisRotatingEqualpriority,roundrobinSpecialmaskInhibitinterruptsfromsomedevices82C55A--InterfaceProgrammableperipheralinterface,40pins(24I/Opins)GeneralI/Omoduleusedwith80386ControlregistercanbesetbyprogramThree-8bitI/Oports(A,C,B)C=>CA+CB,carryingcontrol&statussignalsCAmaybeusedinconjunctionwithportACBmaybeusedinconjunctionwithportB8bitdatalines,2bitaddresslines,etc.ThreemajormodesofoperationsMode0:three8-bitportsMode1:two12-bitportsMode2:astrobedbi-directionalbusconfiguration.7.5DirectMemoryAccessDrawbacksofprogrammedandinterrupt-drivenI/OProgrammedI/OneedstooccupyallCPUtimeInterruptdrivenI/OstillrequiresactiveCPUintervention,

thoughmoreefficientCPUusagethanProgrammedI/O(transferrateislower)Inbothmodes,datatransfermusttraverseCPUTransferrateislimitedCPUistiedupWhenlargevolumesofdataaretransferred,

DMAisamoreefficienttechniqueCh.7-7.5

WhatisDMAExternaltotheCPUAdditionalModule(hardware)onbusDMAcontrollertakesoverfromCPUforI/O

TransferblocksofdatatoorfrommemorywithoutCPUinterventionInfact,DMAisanI/OmodulealsoActasamaseronthebusMemorysystemactslikeslaveDMAgivesexternaldeviceabilitytowritememorydirectlyThreemodesofdatatransferbetweenCPUandDMA:Blocktransfermode

(Monopolisticmode)AnentireblockofdataistransferredinonecontiguoussequenceIfDMAtransfersdata,CPUbedisabledforaduration

untilDMAreleasebusUsefulforloadinganprogramsordatafilesintomemoryCyclestealingmodeDMAusesthebusonlywhenCPUdoesnotneeditorforcingCPUtosuspendoperationtemporarily

DMAtransferonebyteofdata,thenreleasebusDMAinterleavesinstructionsanddatatransfersTransparentmode(alternatemode)DMAandCPUusebusbydivisiontimemultiplexing

Requiremosttime,butmostefficientDMAStructureCounterBufferAddressregisterControl&statuslogicInterruptcontrollerDMAOperationPreprocessing:

CPUtellsDMAcontrollerRead/WriteDeviceaddressStartingaddressofmemoryblockfordataAmountofdatatobetransferredCPUcarriesonwithotherworkDatatransferring:

DMAcontrollerdealswithtransfer(wordbyword)Postprocessing:

DMAcontrollersendsinterruptwhenfinished

DMAtransferprocessThus,CPUisinvolvedonlyatthestartingandendofthetransferDMATransferCycleStealingDMAcontrollertakesoverbusforacycleTransferofonewordofdataNotaninterruptCPUdoesnotswitchcontextCPUsuspendedjustbeforeitaccessesbusi.e.beforeanoperandordatafetchoradatawriteSlowsdownCPUbutnotasmuchasCPUdoingtransferDMAandInterruptBreakpoints

DuringanInstructionCycleDMAConfigurationsSingleBus,detachedDMAcontrollerEachtransferusesbustwiceI/OtoDMAthenDMAtomemoryCPUissuspendedtwiceSingleBus,IntegratedDMAcontrollerControllermaysupport>1deviceEachtransferusesbusonceDMAtomemoryCPUissuspendedonceSeparateI/OBusBussupportsallDMAenableddevicesEachtransferusesbusonceDMAtomemoryCPUissuspendedonce7.6I/OChannelsI/OchannelisanI/OmodulewithitsownprocessorwhichcanexecuteI/OprogramI/OprogramislocatedinmainmemoryInfact,theI/OchannelrepresentsanextensionoftheDMAconceptThus,anI/OchannelhastheabilitytoexecuteI/OinstructionsandcontroltheI/OoperationsFunctionsofI/OChannelsReceivecommandfromCPUMicrocommandLoadI/Oprogramfrommemory,sendcommandstodeviceBuffer,controlandtransferdata,providepathfortransferringReportdevicestatusorinterruptWorkingPrincipleMasterCPUsendsI/OcommandandwaitschannelanddevicereadythenumberofChannelthenumberofdeviceEntryofchannelprogramSizeofdataMasterCPUstartsthechannelandreturnstomainprogramThechannelexecutesI/OprogramtotransferdatabetweenmemoryanddeviceWhendatatransfercompleted,interruptCPUTypesofI/OChannelsSelectorchannelAtanyonetime,onlyonedeviceisselectedtotransferdataHigh-speeddevicesMultiplexorchannelBytemultiplexorchannelRoundrobinbetweendevicesForadevice,onlyonebytedatatransferredForlowspeeddevicesBlockmultiplexorchannelRoundrobinbetweendevicesForadevice,KbytesdatatransferredEvolutionoftheI/OFunctionCPUdirectlycontrolaperipheralAcontrolorI/Omoduleisadded programmedI/OInterrupt-drivenI/ODMADevice--memoryI/OchannelI/Oprocessor,nolocalmemoryI/OprocessorI/Oprocessor+localmemory7.7ExternalInterfaceConnectingdevicestogetherPointtopointDedicatedlinebetweenI/OmoduleandexternaldevicesE.g.keyboard,printer,modem,etc.Pointtomulti-pointexternalbusesExternalmassstorageMultimediadevices(CD-ROMs,video,audio)SerialorparallelPrinter,mouse,keyboard,etc.Disk,tape,etc.WriteoperationfromI/OmoduletoaperipheralI/OmodulesendsacontrolsignalrequestingpermissiontosenddataTheperipheralacknowledgestherequestTheI/OmoduletransfersdataTheperipheralacknowledgesthereceiptofthedataSmallComputerSystemsInterface(SCSI)StandardinterfaceforCD-ROMdrive,audioequipment,externalmassstoragedevicesParallelinterface8,16,32bitdatalinesDaisychainedlocalbus,attachedtoPCIDevicesareindependentDevicescancommunicatewitheachotheraswellashostSCSIVersionsSCSI–1Early1980s,8bit,5MHz,Datarate5MBytes.s-1Sevendevices,daisychainedSCSI-21991,16and32bit,10MHz,Datarate20or40Mbytes.s-18devicesSCSI-3:1995,100MB/s,32devicessupportedSignals&PhasesEventsinSCSItypicallyexperiencefollowingphases:BusfreeArbitration-takecontrolofbusSelecttarget-adevice,CPU,memoryReselection-AllowsreconnectionaftersuspensionCommand-targetrequestingfrominitiatorDatarequestStatusrequestMessagerequest(bothways,e.g.disconnect,commandcomplete)SCSIPhasesAboutSCSIDevicesconnectedtoSCSI：Directaccessdevice,sequentaccessdevicePrinter,processorOpticdriverScanner,mediatransformingdevicesCommunicationdevices，etc.SCSIisastandardSpecificationandisverycomplicatedAllweknowaboveareenoughAboutFireWireHighperformanceserialbus,withasimpleconnector,upto63devicesonsingleportDaisychainortreestructureHotplugging,automaticconfigurationFastLowcost,easytoimplementAlsobeingusedindigitalcameras,VCRandTV

SimpleFireWireConfigurationFireWire3LayerProtocolsPhysicalTransmissionmedium,electricalandsignalingcharacteristicsDataratesfrom25to400MbpsArbitration:priorityLinkTransmissionofdatainpacketsTwotransmissiontypes:AsynchronousIsochronousTransactionRequest-responseprotocolInfiniBandI/OspecificationaimedathighendserversMergerofFutureI/O(Cisco,HP,Compaq,IBM)andNextGenerationI/O(Intel)Version1releasedearly2001Architectureandspec.fordataflowbetweenprocessorandintelligentI/OdevicesIntendedtor