文稿芯片w25q80中文

W25Q80,W25Q16,TableofGENERAL PINCONFIGURATIONW25Q80,W25Q16,TableofGENERAL PINCONFIGURATIONSOIC208- PADCONFIGURATIONWSON6X5- PINDESCRIPTIONSOIC208-MIL,ANDWSON6X5- PINCONFIGURATIONSOIC300- PINDESCRIPTIONSOIC300- Package ChipSelect SerialDataInput,OutputandIOs(DI,DOandIO0,IO1,IO2, WriteProtect HOLD SerialClock BLOCK FUNCTIONAL SPI StandardSPI DualSPI QuadSPI Hold WRITE WriteProtect CONTROLANDSTATUS STATUS WriteEnableLatch BlockProtectBits(BP2,BP1, Top/BottomBlockProtect Sector/BlockProtect StatusRegisterProtect(SRP1, QuadEnable StatusRegisterMemory ManufacturerandDevice InstructionSetTable InstructionSetTable2(Read -2W25Q80,W25Q16,W25Q80,W25Q16,WriteEnable WriteDisable ReadStatusRegister-1(05h)andReadStatusRegister-2 WriteStatusRegister ReadData FastRead FastReadDualOutput FastReadQuadOutput FastReadDualI/O FastReadQuadI/O PageProgram QuadInputPageProgram SectorErase 32KBBlockErase 64KBBlockErase ChipErase(C7h/ EraseSuspend EraseResume Power-down HighPerformanceMode ReleasePower-downorHighPerformanceMode/DeviceID ReadManufacturer/DeviceID ReadUniqueID JEDECID ModeBitReset(FFhor ELECTRICALCHARACTERISTICS AbsoluteMaximum Operating EnduranceandData Power-upTimingandWriteInhibit DCElectrical ACMeasurement ACElectrical ACElectricalCharacteristics SerialOutput Input Hold PACKAGE PublicationReleaseDate:September26,Preliminary-Revision-3W25Q80,W25Q16,8-PinW25Q80,W25Q16,8-PinSOIC208-mil(PackageCode 8-PinPDIP300-mil(PackageCode 8-contact6x5WSON(PackageCode 8-contact6x5WSON 16-PinSOIC300-mil(PackageCode ORDERING ValidPartNumbersandTopSide REVISION -4W25Q80,W25Q16,1.GENERALW25Q80,W25Q16,1.GENERALTheW25Q80(8M-bit),W25Q16(16M-bit),andW25Q32(32M-bit)SerialFlashmemoriesprovideastoragesolutionforsystemswithlimitedspace,pinsandpower.The25QseriesoffersflexibilityandperformancewellbeyondordinarySerialFlashdevices.TheyareidealforcodeshadowingtoRAM,executingcodedirectlyfromDual/QuadSPI(XIP)andstoringvoice,textanddata.Thedevicesoperateonasingle2.7Vto3.6Vpowersupplywithcurrentconsumptionaslowas5mAactiveand1μAforpower-down.Alldevicesareofferedinspace-savingpackages.TheW25Q80/16/32arrayisorganizedinto4,096/8,192/16,384programmablepagesof256-byteseach.Upto256bytescanbeprogrammedatatimeusingthePagePrograminstructions.Pagescanbeerasedingroupsof16(sectorerase),groupsof128(32KBblockerase),groupsof256(64KBblockerase)ortheentirechip(chiperase).TheW25Q80/16/32has256/512/1024erasablesectorsand16/32/64erasableblocksrespectively.Thesmall4KBsectorsallowforgreaterflexibilityinapplicationsthatrequiredataandparameterstorage.(Seefigure2.)TheW25Q80/16/32supportsthestandardSerialPeripheralInterface(SPI),andahighperformanceDual/QuadoutputaswellasDual/QuadI/OSPIusingSPIpins:SerialClock,ChipSelect,SerialDataI/O0(DI),I/O1(DO),I/O2(/WP),andI/O3(/HOLD).SPIclockfrequenciesofupto80MHzaresupportedallowingequivalentclockratesof160MHzforDualOutputand320MHzforQuadOutputwhenusingtheFastReadDual/QuadOutputinstructions.Thesetransferratesarecomparabletothoseof8and16-bitParallelFlashmemories.AHoldpin,WriteProtectpinandprogrammablewriteprotection,withtoporbottomarraycontrol,providefurthercontrolflexibility.Additionally,thedevicesupportsJEDECstandardmanufactureranddeviceidentificationwitha64-bitUniqueSerialNumber.2.FamilyofSpiFlash–W25Q80:8M-bit/1M-byte–W25Q16:16M-bit/2M-byte–W25Q32:32M-bit/4M-byte256-bytesperprogrammableStandard,DualorQuadStandardSPI:CLK,/CS,DI,DO,/WP,DualSPI:CLK,/CS,IO0,IO1,/WP,QuadSPI:CLK,/CS,IO0,IO1,IO2,HighestPerformanceSerialUpto6XthatofordinarySerial80MHzclock160MHzequivalentDual320MHzequivalentQuad40MB/Scontinuousdatatransfer30MB/Srandomaccess(32-byteComparabletoX16ParallelLowPower,WideTemperatureSingle2.7to3.6V4mAactivecurrent,<1μAPower-down-40°Cto+85°CoperatingFlexibleArchitecturewith4KBUniformSectorErase(4K-BlockErase(32Kand64K-Programoneto256Upto100,000erase/write20-yeardataAdvancedSecuritySoftwareandHardwareWrite-ToporBottom,SectororBlockLock-DownandOTP64-BitUniqueIDforeachNoteThesefeaturesareonspecialorder.PleasecontactWinbondfordetails.SpaceEfficient–8-pinSOIC208-–8-padWSON6x5-mm(W25Q80&–16-pinSOIC300-mil(W25Q16&PublicationReleaseDate:September26,Preliminary-Revision-5W25Q80,W25Q16,PINCONFIGURATIONSOIC208-Figure1a.W25Q80,W25Q16,W25Q32PinAssignments,8-pinSOIC208-mil(PackageCodePADCONFIGURATIONWSON6X5-Figure1b.W25Q80,W25Q16PadAssignments,8-padWSON(PackageCodePINDESCRIPTIONSOIC208-MIL,ANDWSON6X5-*1IO0andIO1areW25Q80,W25Q16,PINCONFIGURATIONSOIC208-Figure1a.W25Q80,W25Q16,W25Q32PinAssignments,8-pinSOIC208-mil(PackageCodePADCONFIGURATIONWSON6X5-Figure1b.W25Q80,W25Q16PadAssignments,8-padWSON(PackageCodePINDESCRIPTIONSOIC208-MIL,ANDWSON6X5-*1IO0andIO1areusedforDualandQuad*2IO0–IO3areusedforQuad-6PINPIN1IChipSelect2DODataOutput(DataInputOutput3/WPWriteProtectInput(DataInputOutput45DIDataInput(DataInputOutput6ISerialClock7/HOLDHoldInput(DataInputOutput8PowerW25Q80,W25Q16,PINCONFIGURATIONSOIC300-Figure1c.W25Q16andW25Q32PinAssignments,16-pinSOIC300-mil(PackageCodePINDESCRIPTIONSOIC300-*1IO0andIO1areusedforDualandQuad*2IO0–IO3areusedforQuadPublicationReleaseDate:September26,Preliminary-Revision-7PADPAD1/HOLDHoldInput(DataInputOutput2W25Q80,W25Q16,PINCONFIGURATIONSOIC300-Figure1c.W25Q16andW25Q32PinAssignments,16-pinSOIC300-mil(PackageCodePINDESCRIPTIONSOIC300-*1IO0andIO1areusedforDualandQuad*2IO0–IO3areusedforQuadPublicationReleaseDate:September26,Preliminary-Revision-7PADPAD1/HOLDHoldInput(DataInputOutput2Power3No4No5No6No7IChipSelect8DODataOutput(DataInputOutput9/WPWriteProtectInput(DataInputOutputNoNoNoNoDIDataInput(DataInputOutputISerialClockW25Q80,W25Q16,PackageW25Q80isofferedinan8-pinplastic208-milwidthSOIC(packagecodeSS)and6x5-mmWSON(packagecodeZP).W25Q16isofferedinan8-pinplastic208-milwidthSOIC(packagecodeSS)and6x5-mmWSONasshowninfigure1a,and1b,respectively.TheW25Q16andW25Q32areofferedina16-pinplastic300-milwidthSOIC(packagecodeSF)asshowninfigure1c.Packagediagramsanddimensionsareillustratedattheendofthisdatasheet.ChipSelectTheSPIChipSelect(/CS)pinenablesanddisablesdeviceoperation.When/CSishighthedeviceisdeselectedandtheSerialDataOutput(DO,orIO0,IO1,IO2,IO3)pinsareathighimpedance.Whendeselected,W25Q80,W25Q16,PackageW25Q80isofferedinan8-pinplastic208-milwidthSOIC(packagecodeSS)and6x5-mmWSON(packagecodeZP).W25Q16isofferedinan8-pinplastic208-milwidthSOIC(packagecodeSS)and6x5-mmWSONasshowninfigure1a,and1b,respectively.TheW25Q16andW25Q32areofferedina16-pinplastic300-milwidthSOIC(packagecodeSF)asshowninfigure1c.Packagediagramsanddimensionsareillustratedattheendofthisdatasheet.ChipSelectTheSPIChipSelect(/CS)pinenablesanddisablesdeviceoperation.When/CSishighthedeviceisdeselectedandtheSerialDataOutput(DO,orIO0,IO1,IO2,IO3)pinsareathighimpedance.Whendeselected,thedevicespowerconsumptionwillbeatstandbylevelsunlessaninternalerase,programorstatusregistercycleisinprogress.When/CSisbroughtlowthedevicewillbeselected,powerconsumptionwillincreasetoactivelevelsandinstructionscanbewrittentoanddatareadfromthedevice.Afterpower-up,/CSmusttransitionfromhightolowbeforeanewinstructionwillbeaccepted.The/CSinputmusttracktheVCCsupplylevelatpower-up(see“WriteProtection”andfigure30).Ifneededapull-upresisteron/CScanbeusedtoaccomplishthis.SerialDataInput,OutputandIOs(DI,DOandIO0,IO1,IO2,TheW25Q80/16/32supportstandardSPI,DualSPIandQuadSPIoperation.StandardSPIinstructionsusetheunidirectionalDI(input)pintoseriallywriteinstructions,addressesordatatothedeviceontherisingedgeoftheSerialClock(CLK)inputpin.StandardSPIalsousestheunidirectionalDO(output)toreaddataorstatusfromthedeviceonthefallingedgeCLK.DualandQuadSPIinstructionusethebidirectionalIOpinstoseriallywriteinstructions,addressesordatatothedeviceontherisingedgeofCLKandreaddataorstatusfromthedeviceonthefallingedgeofCLK.QuadSPIinstructionsrequirethenon-volatileQuadEnablebit(QE)inStatusRegister-2tobeset.WhenQE=1the/WPpinbecomesIO2and/HOLDpinbecomesIO3.7.4WriteProtectTheWriteProtect(/WP)pincanbeusedtopreventtheStatusRegisterfrombeingwritten.UsedinconjunctionwiththeStatusRegister’sBlockProtect(SEC,TB,BP2,BP1andBP0)bitsandStatusRegisterProtect(SRP)bits,aportionortheentirememoryarraycanbehardwareprotected.The/WPpinisactivelow.WhentheQEbitofStatusRegister-2issetforQuadI/O,the/WPpin(HardwareWriteProtect)functionisnotavailablesincethispinisusedforIO2.Seefigure1a,1b,and1cforthepinconfigurationofQuadI/Ooperation.HOLDThe/HOLDpinallowsthedevicetobepausedwhileitisactivelyselected.When/HOLDisbroughtlow,while/CSislow,theDOpinwillbeathighimpedanceandsignalsontheDIandCLKpinswillbeignored(don’tcare).When/HOLDisbroughthigh,deviceoperationcanresume.The/HOLDfunctioncanbeusefulwhenmultipledevicesaresharingthesameSPIsignals.The/HOLDpinisactivelow.WhentheQEbitofStatusRegister-2issetforQuadI/O,the/HOLDpinfunctionisnotavailablesincethispinisusedforIO3.Seefigure1a,1b,and1cforthepinconfigurationofQuadI/Ooperation.SerialClockTheSPISerialClockInput(CLK)pinprovidesthetimingforserialinputandoutputoperations.("SeeSPIOperations")-8W25Q80,W25Q16,BLOCKFigure2.W25Q80,W25Q16andW25Q32BlockPublicationReleaseW25Q80,W25Q16,BLOCKFigure2.W25Q80,W25Q16andW25Q32BlockPublicationReleaseDate:September26,Preliminary-Revision-9W25Q80,W25Q16,9.FUNCTIONAL SPIStandardSPIW25Q80,W25Q16,9.FUNCTIONAL SPIStandardSPITheW25Q80/16/32isaccessedthroughanSPIcompatiblebusconsistingoffoursignals:SerialClock(CLK),ChipSelect(/CS),SerialDataInput(DI)andSerialDataOutput(DO).StandardSPIinstructionsusetheDIinputpintoseriallywriteinstructions,addressesordatatothedeviceontherisingedgeofCLK.TheDOoutputpinisusedtoreaddataorstatusfromthedeviceonthefallingedgeCLK.SPIbusoperationModes0(0,0)and3(1,1)aresupported.TheprimarydifferencebetweenMode0andMode3concernsthenormalstateoftheCLKsignalwhentheSPIbusmasterisinstandbyanddataisnotbeingtransferredtotheSerialFlash.ForMode0theCLKsignalisnormallylowonthefallingandrisingedgesof/CS.ForMode3theCLKsignalisnormallyhighonthefallingandrisingedgesof/CS.DualSPITheW25Q80/16/32supportsDualSPIoperationwhenusingthe"FastReadDualOutputandDualI/O"(3BandBBhex)instructions.TheseinstructionsallowdatatobetransferredtoorfromthedeviceattwotothreetimestherateofordinarySerialFlashdevices.TheDualReadinstructionsareidealforquicklydownloadingcodetoRAMuponpower-up(code-shadowing)orforexecutingnon-speed-criticalcodedirectlyfromtheSPIbus(XIP).WhenusingDualSPIinstructionstheDIandDOpinsbecomebidirectionalI/Opins;IO0andIO1.QuadSPITheW25Q80/16/32supportsQuadSPIoperationwhenusingthe"FastReadQuadOutputandFastReadQuadI/O"(6BandEBhexrespectively).TheseinstructionsallowdatatobetransferredtoorfromthedevicefourtosixtimestherateofordinarySerialFlash.TheQuadReadinstructionsofferasignificantimprovementincontinuousandrandomaccesstransferratesallowingfastcode-shadowingtoRAMorexecutiondirectlyfromtheSPIbus(XIP).WhenusingQuadSPIinstructionstheDIandDOpinsbecomebidirectionalIO0andIO1,andthe/WPand/HOLDpinsbecomeIO2andIO3respectively.QuadSPIinstructionsrequirethenon-volatileQuadEnablebit(QE)inStatusRegister-2tobeset.HoldThe/HOLDsignalallowstheW25Q80/16/32operationtobepausedwhileitisactivelyselected/CSislow).The/HOLDfunctionmaybeusefulincaseswheretheSPIdataandclocksignalsaresharedwithotherdevices.Forexample,considerifthepagebufferwasonlypartiallywrittenwhenapriorityinterruptrequiresuseoftheSPIbus.Inthiscasethe/HOLDfunctioncansavethestateoftheinstructionandthedatainthebuffersoprogrammingcanresumewhereitleftoffoncethebusisavailableagain.The/HOLDfunctionisonlyavailableforstandardSPIandDualSPIoperation,notduringQuadSPI.Toinitiatea/HOLDcondition,thedevicemustbeselectedwith/CSlow.A/HOLDconditionwillactivateonthefallingedgeofthe/HOLDsignaliftheCLKsignalisalreadylow.IftheCLKisnotalreadylow/HOLDconditionwillactivateafterthenextfallingedgeofCLK.The/HOLDconditionwillterminateontherisingedgeofthe/HOLDsignaliftheCLKsignalisalreadylow.IftheCLKisnotalreadylowthe-10W25Q80,W25Q16,/HOLDconditionwillterminateafterthenextfallingedgeofCLK.Duringa/HOLDcondition,theSerialDataOutput(DO)ishighimpedance,andSerialDataInput(DI)andSerialClock(CLK)areignored.TheChipSelect(/CS)signalshouldbekeptactive(low)forthefulldurationofthe/HOLDoperationtoavoidresettingtheinternallogicstateofthedevice.WRITEApplicationsthatusenon-volatilememorymusttakeintoconsiderationthepossibilityofnoiseandotheradversesystemconditionsthatmaycompromisedataintegrity.ToaddressthisconcerntheW25Q80/16/32providesseveralmeanstoprotectdatafrominadvertentwrites.WriteProtectW25Q80,W25Q16,/HOLDconditionwillterminateafterthenextfallingedgeofCLK.Duringa/HOLDcondition,theSerialDataOutput(DO)ishighimpedance,andSerialDataInput(DI)andSerialClock(CLK)areignored.TheChipSelect(/CS)signalshouldbekeptactive(low)forthefulldurationofthe/HOLDoperationtoavoidresettingtheinternallogicstateofthedevice.WRITEApplicationsthatusenon-volatilememorymusttakeintoconsiderationthepossibilityofnoiseandotheradversesystemconditionsthatmaycompromisedataintegrity.ToaddressthisconcerntheW25Q80/16/32providesseveralmeanstoprotectdatafrominadvertentwrites.WriteProtectDeviceresetswhenVCCisbelowTimedelaywritedisableafterPower-Writeenable/disableinstructionsandautomaticwritedisableafterprogramandSoftwareandHardware(/WPpin)writeprotectionusingStatus?WriteProtectionusingPower-downLockDownwriteprotectionuntilnextpower-OneTimeProgram(OTP)writeNote1:Thesefeaturesareavailableuponspecialorder.PleasecontactWinbondforUponpower-uporatpower-downtheW25Q80/16/32willmaintainaresetconditionwhileVCCisbelowthethresholdvalueofVWI,(SeePower-upTimingandVoltageLevelsandFigure29).Whilereset,alloperationsaredisabledandnoinstructionsarerecognized.Duringpower-upandaftertheVCCvoltageexceedsVWI,allprogramanderaserelatedinstructionsarefurtherdisabledforatimedelayoftPUW.ThisincludestheWriteEnable,PageProgram,SectorErase,BlockErase,ChipEraseandtheWriteStatusRegisterinstructions.Notethatthechipselectpin(/CS)musttracktheVCCsupplylevelatpower-upuntiltheVCC-minlevelandtVSLtimedelayisreached.Ifneededapull-upresisteron/CScanbeusedtoaccomplishthis.Afterpower-upthedeviceisautomaticallyplacedinawrite-disabledstatewiththeStatusRegisterWriteEnableLatch(WEL)settoa0.AWriteEnableinstructionmustbeissuedbeforeaPageProgram,SectorErase,ChipEraseorWriteStatusRegisterinstructionwillbeaccepted.Aftercompletingaprogram,eraseorwriteinstructiontheWriteEnableLatch(WEL)isautomaticallyclearedtoawrite-disabledstateof0.SoftwarecontrolledwriteprotectionisfacilitatedusingtheWriteStatusRegisterinstructionandsettingtheStatusRegisterProtect(SRP0,SRP1)andBlockProtect(SEC,TB,BP2,BP1andBP0)bits.Thesesettingsallowaportionorallofthememorytobeconfiguredasreadonly.UsedinconjunctionwiththeWriteProtect(/WP)pin,changestotheStatusRegistercanbeenabledordisabledunderhardwarecontrol.SeeStatusRegisterforfurtherinformation.Additionally,thePower-downinstructionoffersanextralevelofwriteprotectionasallinstructionsareignoredexceptfortheReleasePower-downPublicationReleaseDate:September26,Preliminary-Revision-11W25Q80,W25Q16,CONTROLANDSTATUSW25Q80,W25Q16,CONTROLANDSTATUSTheReadStatusRegister-1andStatusRegister-2instructionscanbeusedtoprovidestatusontheavailabilityoftheFlashmemoryarray,ifthedeviceiswriteenabledordisabled,thestateofwriteprotectionandtheQuadSPIsetting.TheWriteStatusRegisterinstructioncanbeusedtoconfigurethedeviceswriteprotectionfeaturesandQuadSPIsetting.WriteaccesstotheStatusRegisteriscontrolledbythestateofthenon-volatileStatusRegisterProtectbits(SRP0,SRP1),theWriteEnableinstruction,andinsomecasesthe/WPpin.10.1STATUS10.1.1BUSYisareadonlybitinthestatusregister(S0)thatissettoa1statewhenthedeviceisexecutingaPageProgram,SectorErase,BlockErase,ChipEraseorWriteStatusRegisterinstruction.DuringthistimethedevicewillignorefurtherinstructionsexceptfortheReadStatusRegisterandEraseSuspendinstruction(seetW,tPP,tSE,tBE,andtCEinACCharacteristics).Whentheprogram,eraseorwritestatusregisterinstructionhascompleted,theBUSYbitwillbeclearedtoa0stateindicatingthedeviceisreadyforfurtherinstructions.10.1.2WriteEnableLatchWriteEnableLatch(WEL)isareadonlybitinthestatusregister(S1)thatissettoa1afterexecutingaWriteEnableInstruction.TheWELstatusbitisclearedtoa0whenthedeviceiswritedisabled.Awritedisablestateoccursuponpower-uporafteranyofthefollowinginstructions:WriteDisable,PageProgram,SectorErase,BlockErase,ChipEraseandWriteStatusRegister.10.1.3BlockProtectBits(BP2,BP1,TheBlockProtectBits(BP2,BP1,BP0)arenon-volatileread/writebitsinthestatusregister(S4,S3,andS2)thatprovideWriteProtectioncontrolandstatus.BlockProtectbitscanbesetusingtheWriteStatusRegisterInstruction(seetWinACcharacteristics).All,noneoraportionofthememoryarraycanbeprotectedfromProgramandEraseinstructions(seeStatusRegisterMemoryProtectiontable).ThefactorydefaultsettingfortheBlockProtectionBitsis0,noneofthearrayprotected.10.1.4Top/BottomBlockProtectThenon-volatileTop/Bottombit(TB)controlsiftheBlockProtectBits(BP2,BP1,BP0)protectfromtheTop(TB=0)ortheBottom(TB=1)ofthearrayasshownintheStatusRegisterMemoryProtectiontable.ThefactorydefaultsettingisTB=0.TheTBbitcanbesetwiththeWriteStatusRegisterInstructiondependingonthestateoftheSRP0,SRP1andWELbits.10.1.5Sector/BlockProtectThenon-volatileSectorprotectbit(SEC)controlsiftheBlockProtectBits(BP2,BP1,BP0)protect4KBSectors(SEC=1)or64KBBlocks(SEC=0)intheTop(TB=0)ortheBottom(TB=1)ofthearrayasshownintheStatusRegisterMemoryProtectiontable.ThedefaultsettingisSEC=0.-12W25Q80,W25Q16,10.1.6StatusRegisterProtect(SRP1,TheStatusRegisterProtectbits(SRP1andSRP0)arenon-volatileread/writebitsinthestatusregister(S8andS7).TheSRPbitscontrolthemethodofwriteprotection:softwareprotection,hardwareprotection,powersupplylock-downoronetimeprogrammable(OTP)protection.Thesefeaturesareavailableuponspecialorder.PleasecontactW25Q80,W25Q16,10.1.6StatusRegisterProtect(SRP1,TheStatusRegisterProtectbits(SRP1andSRP0)arenon-volatileread/writebitsinthestatusregister(S8andS7).TheSRPbitscontrolthemethodofwriteprotection:softwareprotection,hardwareprotection,powersupplylock-downoronetimeprogrammable(OTP)protection.Thesefeaturesareavailableuponspecialorder.PleasecontactWinbondforWhenSRP1,SRP0=(1,0),apower-down,power-upcyclewillchangeSRP1,SRP0to(0,0)10.1.7QuadEnableTheQuadEnable(QE)bitisanon-volatileread/writebitinthestatusregister(S9)thatallowsQuadoperation.WhentheQEbitissettoa0state(factorydefault)the/WPpinand/Holdareenabled.WhentheQEpinissettoa1theQuadIO2andIO3pinsareenabled.WARNING:TheQEbitshouldneverbesettoa1duringstandardSPIorDualSPIoperationif/WPor/HOLDpinsaretieddirectlytothepowersupplyorPublicationReleaseDate:September26,Preliminary-Revision-1300X/WPpinhasnocontrol.TheStatusregistercanbewrittentoafteraWriteEnableinstruction,WEL=1.[FactoryDefault]010When/WPpinislowtheStatusRegisterlockedandcannotbewrittento.011When/WPpinishightheStatusregisterisunlockedandcanbewrittentoafteraWriteEnableinstruction,WEL=1.10XPowerSupplyLock-StatusRegisterisprotectedandcannotbewrittentoagainuntilthenextpower-down,power-upcycle.(2)11XStatusRegisterispermanentlyprotectedandcannotbewrittento.W25Q80,W25Q16,Figure3a.W25Q80,W25Q16,Figure3a.StatusRegister-Figure3b.StatusRegister--14W25Q80,W25Q16,StatusRegisterMemoryPublicationReleaseDate:September26,Preliminary-Revision-15STATUSW25Q32(32M-BIT)MEMORYXX000000013F0000h-Upper0001062and3E0000h-Upper0001160thru3C0000h-Upper0010056thru380000h-Upper0010148thru300000h-Upper0011032thru200000h-Upper010010000000h-Lower010100and000000h-Lower010110thruW25Q80,W25Q16,StatusRegisterMemoryPublicationReleaseDate:September26,Preliminary-Revision-15STATUSW25Q32(32M-BIT)MEMORYXX000000013F0000h-Upper0001062and3E0000h-Upper0001160thru3C0000h-Upper0010056thru380000h-Upper0010148thru300000h-Upper0011032thru200000h-Upper010010000000h-Lower010100and000000h-Lower010110thru000000h-Lower011000thru000000h-Lower011010thru000000h–Lower011100thru000000h–LowerXX1110thru000000h–100013FF000h–Top100103FE000h–Top100113FC000h–Top1010X3F8000h–Top110010000000h–Bottom110100000000h–Bottom110110000000h–Bottom1110X0000000h–BottomW25Q80,W25Q16,-16STATUSW25Q16(16M-BIT)MEMORYXX000000011F0000h-Upper0001030and1E0000h-Upper0001128thru1C0000h-Upper0010024thru180000h-Upper0010116thru100000h-Upper010010000000h-Lower010100and000000h-Lower010110thru000000h-Lower011000thru000000h-W25Q80,W25Q16,-16STATUSW25Q16(16M-BIT)MEMORYXX000000011F0000h-Upper0001030and1E0000h-Upper0001128thru1C0000h-Upper0010024thru180000h-Upper0010116thru100000h-Upper010010000000h-Lower010100and000000h-Lower010110thru000000h-Lower011000thru000000h-Lower011010thru000000h–LowerXX11X0thru000000h–100011FF000h–Top100101FE000h–Top100111FC000h–Top1010X1F8000h–Top110010000000h–Bottom110100000000h–Bottom110110000000h–Bottom1110X0000000h–BottomW25Q80,W25Q16,1.x=don’tPublicationReleaseDate:September26,Preliminary-Revision-17STATUSW25Q80(8M-BIT)MEMORYXX000000010F0000h-Upper0001014and0E0000h-Upper0001112thru0C0000h-Upper001008thru080000h-Upper010010000000h-Lower010100and000000h-Lower010110thruW25Q80,W25Q16,1.x=don’tPublicationReleaseDate:September26,Preliminary-Revision-17STATUSW25Q80(8M-BIT)MEMORYXX000000010F0000h-Upper0001014and0E0000h-Upper0001112thru0C0000h-Upper001008thru080000h-Upper010010000000h-Lower010100and000000h-Lower010110thru000000h-Lower011000thru000000h-LowerXX11X0thru000000h–100010FF000h–Top100100FE000h–Top100110FC000h–Top1010X0F8000h–Top110010000000h–Bottom110100000000h–Bottom110110000000h–Bottom1110X0000000h–BottomW25Q80,W25Q16,10.2TheinstructionsetoftheW25Q80/16/32consistsoffifteenbasicinstructionsthatarefullycontrolledthroughtheSPIbus(seeInstructionSettable).InstructionsareinitiatedwiththefallingedgeofChipSelect(/CS).ThefirstbyteofdataclockedintotheDIinputprovidestheinstructioncode.DataontheDIinputissampledontherisingedgeofclockwithmostsignificantbit(MSB)first.Instructionsvaryinlengthfromasinglebytetoseveralbytesandmaybefollowedbyaddressbytes,databytes,dummybytes(don’tcare),andinsomecases,acombination.Instructionsarecompletedwiththerisingedgeofedge/CS.Clockrelativetimingdiagramsforeachinstructionareincludedinfigures4through19.Allreadinstructionscanbecompletedafteranyclockedbit.However,allinstructionsthatWrite,ProgramorErasemustcompleteonabyteboundary(CSdrivenhighafterafull8-bitshavebeenclocked)otherwisetheinstructionwillbeterminated.Thisfeaturefurtherprotectsthedevicefrominadvertentwrites.Additionally,whilethememoryisbeingprogrammedorerased,orwhentheStatusRegisterisbeingwritten,allinstructionsexceptforReadStatusRegisterwillbeignoreduntiltheprogramorerasecyclehascompleted.ManufacturerandDevice-18MANUFACTURERW25Q80,W25Q16,10.2TheinstructionsetoftheW25Q80/16/32consistsoffifteenbasicinstructionsthatarefullycontrolledthroughtheSPIbus(seeInstructionSettable).InstructionsareinitiatedwiththefallingedgeofChipSelect(/CS).ThefirstbyteofdataclockedintotheDIinputprovidestheinstructioncode.DataontheDIinputissampledontherisingedgeofclockwithmostsignificantbit(MSB)first.Instructionsvaryinlengthfromasinglebytetoseveralbytesandmaybefollowedbyaddressbytes,databytes,dummybytes(don’tcare),andinsomecases,acombination.Instructionsarecompletedwiththerisingedgeofedge/CS.Clockrelativetimingdiagramsforeachinstructionareincludedinfigu