EDA技術(shù)與Verilog設(shè)計(jì)第六章課后習(xí)題部分答案PPT課件

1 6 11 6 11試編寫求補(bǔ)碼的Verilog程序 輸入是帶符號(hào)的8位二進(jìn)制數(shù)modulewytest data in data out 習(xí)題6 11input 7 0 data in output 7 0 data out reg 7 0 data out always data in beginif data in 7 正數(shù)負(fù)數(shù)判斷 從最高是否為1來(lái)判斷data out data in 1 8 h80 elsedata out data in endendmodule 2 6 11仿真波形 8A 原碼表示的十進(jìn)制數(shù) 100A 十進(jìn)制數(shù)10B6 原碼表示的十進(jìn)制數(shù) 5436 十進(jìn)制數(shù)5380 原碼表示的十進(jìn)制數(shù)128 3 6 12 6 12編寫兩個(gè)四位二進(jìn)制數(shù)相減的verilog程序modulewytest opr1 opr2 out data 完成Opr1 opr2的運(yùn)算input 3 0 opr1 opr2 output 4 0 out data reg 3 0 out regcout function 3 0 abs input 3 0 data case data 3 1 b0 abs data 1 b1 abs data 1 對(duì)負(fù)數(shù)求絕對(duì)值 按位取反再加1endcaseendfunction 4 6 12 always opr1oropr2 case opr1 3 opr2 3 2 b00 cout out opr1 opr2 兩個(gè)正數(shù)相減2 b01 cout out opr1 abs opr2 正數(shù)減負(fù)數(shù) 化為加法運(yùn)算2 b10 cout out abs opr1 opr2 負(fù)數(shù)減正數(shù) 化為加法再取反2 b11 cout out abs opr2 abs opr1 負(fù)數(shù)相減 化為絕對(duì)值相減 順序調(diào)換 endcaseassignout data cout out endmodule 5 6 12 6 12仿真波形 6 6 13 6 13有一個(gè)比較電路 當(dāng)輸入的一位BCD碼大于4時(shí) 輸出1 否則輸出0 modulewytest bcd in out input 3 0 bcd in outputout assignout bcd in 4 1 0 endmodule 7 6 13 仿真波形 8 6 13 modulewytest bcd in out 習(xí)題6 13input 3 0 bcd in outputout assignout bcd in 4 1 0 regout always bcd in if bcd in 4 0 out 1 elseout 0 endmodule 9 6 13 10 6 14 試編寫一個(gè)實(shí)現(xiàn)3輸入與非門的verilog程序 modulewytest a o input 2 0 a outputo nandnand3 o a 0 a 1 a 2 endmodule 11 6 14 12 6 15 6 15設(shè)計(jì)74138譯碼器電路 13 6 15 modulewytest s1 s2 in out inputs1 input 1 0 s2 input 2 0 in output 7 0 out reg 8 0 out always s1ors2orin beginif s1 0 out 8 hff elseif s2 0 s2 1 out 8 hff elsecase in 3 d0 out 8 b11111110 3 d1 out 8 b11111101 3 d2 out 8 b11111011 3 d3 out 8 b11110111 3 d4 out 8 b11101111 3 d5 out 8 b11011111 3 d6 out 8 b10111111 3 d7 out 8 b01111111 endcaseendendmodule 14 6 15 15 6 16 CO Q3Q2Q1Q0CTT 注意 異步清零 同步置位 6 16設(shè)計(jì)一個(gè)74161的電路 16 6 16 modulewytest reset load ctt ctp clk data in out co 習(xí)題6 16inputreset load ctt ctp clk input 3 0 data in output 3 0 out outputco reg 3 0 out regco always posedgeclkornegedgereset if reset beginout 4 b0 co 1 b0 endelseif load out data in elseif ctt out out elseif ctp out out elsebeginout out 1 if out 14 co 1 elseco 0 endendmodule 17 6 16 18 四級(jí)流水線實(shí)現(xiàn)的32位加法器 modulewytest clk a b sum cout input 31 0 a b inputclk output 31 0 sum outputcout 最后輸出的結(jié)果reg 31 0 sum regcout 第一級(jí)流水線的輸出reg 7 0 fist sum regfirst cout 第一級(jí)流水線要緩存的數(shù)據(jù) 未用的數(shù)據(jù)緩存reg 7 0 first a 31 24 first a 23 16 first a 15 8 reg 7 0 first b 31 24 first b 23 16 first b 15 8 19 四級(jí)流水線實(shí)現(xiàn)的32位加法器 第二級(jí)流水線的輸出reg 7 0 second sum regsecond cout 第二級(jí)流水線要緩存的數(shù)據(jù) 未用的數(shù)據(jù)緩存reg 7 0 second a 31 24 second a 23 16 reg 7 0 second b 31 24 second b 23 16 第一級(jí)流水線計(jì)算結(jié)果緩存reg 7 0 first sum 1 第一級(jí)流水線計(jì)算結(jié)果第一次緩存 第三級(jí)流水線輸出reg 7 0 third sum regthird cout 第三級(jí)流水線要緩存的數(shù)據(jù) 未用的數(shù)據(jù)緩存reg 7 0 third a 31 24 reg 7 0 third b 31 24 第一級(jí) 第二級(jí)流水線計(jì)算結(jié)果緩存reg 7 0 first sum 2 第一級(jí)流水線計(jì)算結(jié)果第二次緩存 reg 7 0 second sum 1 第二級(jí)流水線計(jì)算結(jié)果第一次緩存 20 四級(jí)流水線實(shí)現(xiàn)的32位加法器 第一級(jí)流水線always posedgeclk begin first cout fist sum a 7 0 b 7 0 cout first a 31 24 a 31 24 first b 31 24 b 31 24 first a 23 16 a 23 16 first b 23 16 b 23 16 first a 15 8 a 15 8 first b 15 8 b 15 8 end 第二級(jí)流水線always posedgeclk begin second cout second sum first a 15 8 first b 15 8 first cout second a 31 24 first a 31 24 second b 31 24 first b 31 24 second a 23 16 first a 23 16 second b 23 16 first b 23 16 first sum 1 fist sum end 21 四級(jí)流水線實(shí)現(xiàn)的32位加法器 第三級(jí)流水線always posedgeclk begin third cout third sum second a 23 16 second b 23 16 second cout third a 31 24 second a 31 24 third b 31 24 second b 31 24 first sum 2 first sum 1 second sum 1 second sum end 第四級(jí)流水線always posedgeclk begin cout sum 31 24 third a 31 24 third b 31 24 third cout sum 23 0 third sum second sum 1 first sum 2 endendmodule 22 四級(jí)流水線實(shí)現(xiàn)的32位加法器 23 8x8乘法器實(shí)現(xiàn) modulewytest out a b clk input 7 0 a b inputclk output 15 0 out reg 15 0 out reg 3 0 firsta firstb reg 3 0 seconda secondb wire 7 0 outa outb outc outd always posedgeclk beginfirsta 3 0 a 7 4 seconda 3 0 a 3 0 firstb 3 0 b 7 4 secondb 3 0 b 3 0 end mul4x4m1 outa firsta firstb clk m2 outb seconda firstb clk m3 outc firsta secondb clk m4 outd seconda secondb clk always posedgeclk out outa 8 outb 4 outc 4 outd endmodule 24 8x8乘法器實(shí)現(xiàn) 用另一種方法實(shí)現(xiàn) 將8位數(shù)字分成4段 每段兩位 那么操作數(shù)可表示如下 A A1X26 A2X24 A3X22 A4B B1X26 B2X24 B3X22 B4AXB A1X26 A2X24 A3X22 A4 X B1X26 B2X24 B3X22 B4 上式展開(kāi)后 要做16次2X2的乘法 調(diào)用16次lookup函數(shù)然后再做移位相加的處理 25 7 5編寫4位并 串轉(zhuǎn)換電路 modulewytest clk rst in out inputclk rst input 3 0 in outputout regout reg 1 0 i always posedgeclk beginif rst begini 2 d0 out 1 d0 endelseif i 3 beginout in i i i 1 endend 26 模為9的占空比50 的奇數(shù)分頻 modulewytest RESET CLK COUT inputCLK RESET outputCOUT reg 3 0 m n wireCOUT regCOUT1 COUT2 assignCOUT COUT1 COUT2 always posedgeCLK beginif RESET beginCOUT1 0 輸出信號(hào)初態(tài)為0m 0 計(jì)數(shù)初值為0end elseif RESET beginif m 8 n 1beginm 0 endelsem m 1 if m 3 N 2 1 5COUT1 COUT1 elseif m 7 N 2COUT1 COUT1 endend 27 always negedgeCLK beginif RESET beginCOUT2 0 n 0 end elseif RESET beginif n 8 beginn 0 endelsen n 1 if n 3 COUT2 COUT2 elseif n 7 COUT2 COUT2 endendEndmodule 模為9的占空比50 的奇數(shù)分頻 28 模為9 3的小數(shù)分頻 分頻方法 9分頻7次 10分頻3次 modulefdiv8 1 clk in rst clk out inputclk in rst outputclk out regclk out reg 3 0 cnt1 cnt1計(jì)8分頻的次數(shù)reg 3 0 cnt2 cnt2為兩個(gè)分頻器的計(jì)數(shù)值always posedgeclk inorposedgerst beginif rst begincnt1 0 cnt2 0 clk out 0 endelseif cnt1 7 9分頻7次beginif cnt2 8 9分頻的前8個(gè)脈沖的處理begincnt2 cnt2 1 clk out 0 endelse 處理最后一個(gè)輸入脈沖begincnt2 0 clk out 1 cnt1 cnt1 1 endend 29 模為9 3的小數(shù)分頻 elseif cnt1 10 beginif cnt2 9 10分頻的前9個(gè)脈沖處理begincnt2 cnt2 1 clk out 0 endelsebegincnt2 0 clk out 1 if cnt1 9 cnt1 0 elsecnt1 cnt1 1 endendendendmodule 30 習(xí)題10 3 1001 二進(jìn)制序列檢測(cè)器 S0 S1 S2 S3 1 0 0 0 0 0 0 0 1 1 1 0 1 0 0