中科院_段成華_專用集成電路設(shè)計(jì)_作業(yè)4詳解

1、Assignment 41. For the cascaded inverter pair shown below, using HSPICE and TSMC 0.18 m CMOS technology model with 1.8 V power supply and assuming Ln=200 nm, Wn=400 nm, ADn=0.2 pm2, ASn=0.2 pm2, Reqn=18 K for the NMOS device and Lp=200 nm, Wp=800 nm, ADp=0.4 pm2, ASp=0.4 pm2, Reqp=45 K for the PMOS

2、device, CW=0.01 fF, please (1) measure the parasitic capacitances: Cdg1, Cdg2, Cdb1, Cdb2, Cg3, and Cg4 by HSPICE simulation;(2) according to the values of these capacitances, compute the propagation delays: tPLH, tPHL, and tPD respectively;(3) measure the propagation delay tPD by HSPICE simulation,

3、 and compare the value with the one just computed from (2).(Hint: For details of how to measure the parasitic capacitances of MOSFET devices in HSPICE, please refer to the “MOSFET Capacitance Models” section of the HSPICE Reference Manual: MOSFET Models, version A-2007.09, Sept. 2007, Synopsys. )Sol

4、ution:(1) Codes$ The cascaded inverter parasitic capacitances calculation.lib D:Program Files (x86)synopsysHspice_D-2010.03-SP1MM018.L TT* Set 0.18um library*mn d g 0 b NCH l=0.2u w=0.4u ad=0.2e-12 pd=0.4u as=0.2e-12 ps=0.4u*mn d g 0 b NCH l=0.2u w=0.4u ad=0.2e-12 pd=1.4u as=0.2e-12 ps=1.4u *three-s

5、idevdd vdd 0 1.8*vin n1 0 0.9 pulse 0.1 1.7 150p 50p 50p 200p 600p*vin n1 0 0.9 pulse 0.0 1.8 150p 5p 5p 290p 600p* m1 n2 n1 vdd vdd PCH l=0.2u w=0.8u ad=0.4p2 pd=0.8u as=0.4p2 ps=0.8um1 n2 n1 vdd vdd PCH l=0.2u w=0.8u ad=0.4e-12 pd=0.8u as=0.4e-12 ps=0.8u* m2 n2 n1 0 0 NCH l=0.2u w=0.4u ad=0.2p2 pd

6、=0.4u as=0.2p2 ps=0.4um2 n2 n1 0 0 NCH l=0.2u w=0.4u ad=0.2e-12 pd=0.4u as=0.2e-12 ps=0.4um3 n3 n2 vdd vdd PCH l=0.2u w=0.8u ad=0.4p2 pd=0.8u as=0.4p2 ps=0.8um4 n3 n2 0 0 NCH l=0.2u w=0.4u ad=0.2p2 pd=0.4u as=0.2p2 ps=0.4uc1 n2 0 0.01f*c2 n3 0 0.01f*vd d 0 1.8vin n1 0 1.8 ac .1*vb b 0 0.ac dec 1 1.5

7、9155e6 1.59155e7* Perform a frequency sweep by 1-point per decade from 1.59 to 15.9 MHz.print CGD1=par(-lx19(m2) CGD2=par(-lx19(m1) CDB1=par(-lx22(m2)+CDB2=par(-lx22(m1) CG3=lx18(m4) CG4=lx18(m3)*CGGn=lx18(mn)=cgtot=cgs+cgd+cgb, *CDDn=lx33(mn)=cdtot=cgd+cdb,*CGDn=par(-lx19(mn)=cgd, *CDGn=par(-lx32(m

8、n)=cdg,*CDBn=par(-lx22(mn)=cdb*CSS,CBB are not printed out because Source and Bulk are grounded. .print ig_imag=ii2(mn) id_imag=ii1(mn)*ii(mn) prints the imaginary part of the current through mn.*first “i”: current; second “i”: imaginary*ig_imag: imaginary gate current; id_imag: imaginary drain curr

9、ent.alter*vg g 0 1.8vin in 0 0 ac .1.endResults:圖1 仿真的寄生電容值圖2 仿真的寄生電容圖示(2) 由(1)中所得的電容值可得CL= Cdg1+Cdg2+ Cdb1+Cdb2+ Cg3+Cg4+Cw=3.75fFtPHL=0.69*Reqn*CL=0.69*(18/(400/200)k *3.75fF23.29pstPLH=0.69*Reqp*CL=0.69*(45/(800/200)k *3.75fF29.11pstPD=(1/2)*( tPHL+ tPLH)=26.20ps(3) Codes$ Bsim3demo3 - the measur

10、e statement for inverter.tran 5p 2000p.lib D:Program Files (x86)synopsysHspice_D-2010.03-SP1MM018.L TT* Set TSMC 0.18um library*.model pch PMOS level=49 version = 3.1*.model nch NMOS level=49 version = 3.1.options list node post measout* Option List: Prints a list of netlist elements, node connectio

11、ns, and values for components, voltage and current sources, parameters, and more.* Option Node: Prints a node cross-reference table.* Option Post: Saves simulation results for viewing by an interactive waveform viewer.* Option Measout: Outputs .MEASURE statement values and sweep parameters into an A

12、SCII file.vdd vdd 0 1.8*vin n1 0 0.9 pulse 0.1 1.7 150p 50p 50p 200p 600pvin n1 0 0.9 pulse 0.0 1.8 150p 5p 5p 290p 600p* m1 n2 n1 vdd vdd PCH l=0.2u w=0.8u ad=0.4p2 pd=0.8u as=0.4p2 ps=0.8um1 n2 n1 vdd vdd PCH l=0.2u w=0.8u ad=0.4e-12 pd=0.8u as=0.4e-12 ps=0.8u* m2 n2 n1 0 0 NCH l=0.2u w=0.4u ad=0.

13、2p2 pd=0.4u as=0.2p2 ps=0.4um2 n2 n1 0 0 NCH l=0.2u w=0.4u ad=0.2e-12 pd=0.4u as=0.2e-12 ps=0.4um3 n3 n2 vdd vdd PCH l=0.2u w=0.8u ad=0.4p2 pd=0.8u as=0.4p2 ps=0.8um4 n3 n2 0 0 NCH l=0.2u w=0.4u ad=0.2p2 pd=0.4u as=0.2p2 ps=0.4uc1 n2 0 0.01f* c2 n3 0 0.01f.param tdval=50p tstop=2000p.meas tran tphl

14、trig v(n1) val=0.9 td=tdval rise=2+targ v(n2) val=0.9 fall=2* rise=2 specifies to measure the v(n1) voltage only on the first two rising edges of the waveform. * trig v(n1) val=0.9 indicates to trigger when the voltage on the rising edge voltage is 0.9.* td=tdval : time at which measurement starts.*

15、 tphl is the user-defined variable name for the measurement(the time difference between TRIG and TARG events).meas tran tplh trig v(n1) val=0.9 td=tdval fall=2+targ v(n2) val=0.9 rise=2.meas tran vmax max v(n2) from=tdval to=tstop.meas tran vmin min v(n2) from=tdval to=tstop.meas tran trise trig v(n

16、2) val=vmin+.1*vmax td=tdval+rise=1 targ v(n2) val=.9*vmax rise=1.meas tran tfall trig v(n2) val=.9*vmax td=tdval+fall=2 targ v(n2) val=vmin+.1*vmax fall=2.print tran v(n1) v(n2) v(n3).endResults:圖3 仿真延時(shí)值a）仿真所得輸入輸出b) tPHL(約為19ps)放大后c) tPLH(約為26ps)放大后圖4 仿真延時(shí)示意圖由上圖的結(jié)果可以看出tPD=(1/2)*( tPHL+ tPLH)=22.53p

17、s(2)和(3)對比可知，兩者僅相差，3.67ps.2. The following figure shows a master-slave positive edge-triggered d-flip-flop. The master and slave latches are transparent. By using HSPICE circuit simulation tool with the tsmc 0.18 m CMOS technology library, please(1) measure the timing parameters of tSETUP, tCO and t

18、HOLD;(2) according to the results of (1), verify if the theoretical equations tSETUP = 3tP_INV + tP_TX, tCO = tP_INV + tP_TX, and tHOLD = 0 are satisfied.Solution(1) Code* bsim3dlatch.sp- cmos d-flip-flop, transparent.lib D:Program Files (x86)synopsysHspice_D-2010.03-SP1MM018.L TT* Set TSMC 0.18um l

19、ibrary.option list node post.tran 50p 6000p* Starts a transient analysis that simulates a circuit at a specific time.* format: .TRAN tstep1 tstop1 .probe tran+ clock=par(v(clck)+ data=par(v(d)+ q=par(v(q)* Use this command to save output variables to interface and graph data* files. The parameter ca

20、n be a node voltage or a reasonable expression.ic v(q)=0 $ set initial value. * The node voltages that you specify in the .IC statement are fixed to* determine the DC operating point. They are used only in the first * iteration to set an initial guess for the DC operating point analysis.* waveformsv

21、data d gnd pulse(0,1.8 200p,40p,40p 1100p,2400p)* pulse( v1 v2 td tr tf pw per )vclk clck gnd pulse(0,1.8 300p,40p,40p 600p,1200p)vclkn clckn gnd pulse(1.8,0 300p,40p,40p 600p,1200p)* top: d-latch* xclkinv clck clckn inv $ enable if asymmetric (overlapping) positive* and negative clocks are usedxdla

22、tch d clck clckn q qb dlatchcw q gnd .1f $ add wire delay*xdlatch1 qb clck clckn q1 qb1 dlatch1cw1 q1 gnd .1f $ add wire delay* macro definitions* n-channel mosfet* drain gate source.subckt nmos n1 n2 n3mn n1 n2 n3 gnd NCH l=0.2u w=0.4u ad=0.2p2 pd=0.4u as=0.2p2 ps=0.4u .ends nmos* p-channel mosfet* drain gate source .subckt pmos n1 n2 n3vcc vcc gnd 1.8mp n1 n2 n3 vcc PCH l=0.2u w=0.8u ad=0.4p2 pd=0.8u as=0.4p2 ps=0.8u.ends pmos*.subckt tgate in out clk clknxmn in clk out nmosxmp in clkn out pmos.ends tgate*.subckt inv in outvcc vcc gnd 1.8xmn out in gnd nmosxmp out in v