VHDL電子鐘實(shí)驗(yàn)報(bào)告

PAGEPAGE2期末大作業(yè)課程設(shè)計(jì)實(shí)驗(yàn)報(bào)告設(shè)計(jì)題目：基于VHDL電子鐘的設(shè)計(jì)目錄概述…………31.1目的……………31.2課程設(shè)計(jì)的要求和功能………3二、總結(jié)…………..32.1課程設(shè)計(jì)進(jìn)行過程及步驟……32.2所遇到的問題，如何解決問題……………….152.3體會(huì)收獲以及建議…………….153.4參考資料（書，網(wǎng)絡(luò)資料）………………….15三、教師評語………16四、成績……………16概述1.1目的1.基于CPLD系統(tǒng)模塊板，設(shè)計(jì)一個(gè)電子鐘。來熟悉CPLD的工作原理以及對VHDL的使用。2.通過設(shè)計(jì)出一個(gè)電子鐘具有校時(shí)功能，來鞏固分頻，鍵盤掃描，計(jì)數(shù)，動(dòng)態(tài)掃描等知識(shí)內(nèi)容。1.2課程設(shè)計(jì)的要求和功能設(shè)計(jì)一個(gè)電子鐘，能進(jìn)行正常的時(shí)分秒計(jì)時(shí)功能，分別有六個(gè)數(shù)碼管顯示24小時(shí)，60分鐘，60秒的計(jì)數(shù)器顯示。利用實(shí)驗(yàn)箱系統(tǒng)上的按鍵實(shí)現(xiàn)“校時(shí)”、“校分”功能：（1）按下“SA”鍵時(shí)，計(jì)時(shí)器快速遞增，按24小時(shí)循環(huán)，進(jìn)行時(shí)校正；（2）按下“SB”鍵時(shí)，計(jì)分器快速遞增，按60分循環(huán)，進(jìn)行分校正（3）按下“SC”鍵時(shí)，秒清零，進(jìn)行秒校正；二、總結(jié)2.1課程設(shè)計(jì)進(jìn)行及步驟1．設(shè)計(jì)提示系統(tǒng)框圖見下動(dòng)態(tài)顯示電路動(dòng)態(tài)顯示電路M24計(jì)數(shù)器M60計(jì)數(shù)器M60計(jì)數(shù)器控制器校時(shí)電路控制輸入2．系統(tǒng)結(jié)構(gòu)設(shè)計(jì)描述（1）系統(tǒng)頂層文件1.頂層原理圖見下2.各個(gè)模塊的解釋（1）五個(gè)輸入量clk50MHz,SA,SB,SC,reset：其中clk50MHz為總體系統(tǒng)提供時(shí)鐘，并且經(jīng)過分頻來分別對電子鐘模塊提供時(shí)鐘，產(chǎn)生一秒一秒的進(jìn)位信號(hào)，對顯示模塊的計(jì)數(shù)器提供時(shí)鐘實(shí)現(xiàn)顯示模塊的掃描功能，對按鍵去抖動(dòng)提供時(shí)鐘，實(shí)現(xiàn)鍵盤掃描的功能。SA,SB,SC用來控制按鍵，實(shí)現(xiàn)按鍵控制，SA是實(shí)現(xiàn)“時(shí)”加一，SB是實(shí)現(xiàn)“分”加一，SC是實(shí)現(xiàn)“秒”清零。Reset是來控制按鍵功能的使能。（2）按鍵功能模塊三個(gè)輸入chos,date0,date1的功能是：chos接受來自按鍵的信號(hào)，若按鍵按下，則將date0的內(nèi)容，也就是通過按鍵產(chǎn)生的脈沖來控制電子鐘進(jìn)行加一，若按鍵沒有按下，則將“秒”分頻信號(hào)接入電子鐘的clk計(jì)數(shù)輸入端，通過時(shí)鐘脈沖來控制電子鐘。（3）電子鐘計(jì)數(shù)模塊有5個(gè)輸入ci,nreset,load,clk,d[7..0]，作用分別是ci是使能端，直接接高電位，nreset是復(fù)位，load和d[7..0]是用來置數(shù)的，clk提供計(jì)數(shù)時(shí)鐘，也就是一秒一個(gè)脈沖。輸出端有三個(gè)，co是進(jìn)位功能，只有“秒”和“分”模塊有效，qh[3..0],ql[3..0]是分位的數(shù)字輸出端，一個(gè)是十位，一個(gè)是個(gè)位。（4）顯示模塊輸入端有qcnt接受來自計(jì)數(shù)器的計(jì)數(shù)實(shí)現(xiàn)顯示掃描，d0h,d1h,d0m,d1m,d0s,d1s分別是接收的來自“秒”“分”“時(shí)”個(gè)位十位的數(shù)據(jù)，seg輸出LCD的段掃描結(jié)果，SCAN輸出LCD位掃描結(jié)果。（2）系統(tǒng)各個(gè)模塊的VHDL程序1．顯示模塊Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;Useieee.std_logic_arith.all;entitydisplayisport(qcnt:INintegerrange0to7;--計(jì)數(shù)值輸入d0h,d1h,d0m,d1m,d0s,d1s:INintegerrange0to9;--分位得到的十位數(shù)和個(gè)位數(shù)seg:OUTstd_logic_vector(6downto0);--7位段碼輸出scan:OUTstd_logic_vector(7downto0)--8為位碼輸出);enddisplay;architectureaofdisplayissignaldata:integerrange0to10;beginprocess(qcnt,d0h,d1h,d0m,d1m,d0s,d1s)begincaseqcntiswhen0=>scan<="11111110";data<=d0h;when1=>scan<="11111101";data<=d1h;when2=>scan<="11111011";data<=10;when3=>scan<="11110111";data<=d0m;when4=>scan<="11101111";data<=d1m;when5=>scan<="11011111";data<=10;when6=>scan<="10111111";data<=d0s;whenothers=>scan<="01111111";data<=d1s;endcase;endprocess;process(data)begincasedataiswhen0=>seg<="0111111";--0when1=>seg<="0000110";--1when2=>seg<="1011011";--2when3=>seg<="1001111";--3when4=>seg<="1100110";--4when5=>seg<="1101101";--5when6=>seg<="1111101";--6when7=>seg<="0000111";--7when8=>seg<="1111111";--8when9=>seg<="1100111";--9when10=>seg<="1000000";--whenothers=>seg<="0000000";endcase;endprocess;enda;動(dòng)態(tài)顯示計(jì)數(shù)器部分：LIBRARYieee;USEieee.std_logic_1164.all;useieee.std_logic_unsigned.all;--EntityDeclarationENTITYqcnt_displayIS --{{ALTERA_IO_BEGIN}}DONOTREMOVETHISLINE! PORT ( clk:INSTD_LOGIC; qcnt:bufferSTD_LOGIC_VECTOR(2downto0) ); --{{ALTERA_IO_END}}DONOTREMOVETHISLINE! ENDqcnt_display;--ArchitectureBodyARCHITECTUREcnt_architectureOFqcnt_displayISBEGINPROCESS(clk) BEGIN IF(clk'EVENTANDclk='1')THEN qcnt<=qcnt+1; ENDIF; ENDPROCESS;ENDcnt_architecture;2.分位計(jì)數(shù)模塊“秒”，“分”部分：LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_unsigned.all;--EntityDeclarationENTITYcounter60IS --{{ALTERA_IO_BEGIN}}DONOTREMOVETHISLINE! PORT ( ci:instd_logic; nreset:INSTD_LOGIC:='1'; load:INSTD_LOGIC; clk:INSTD_LOGIC; d:instd_logic_vector(7downto0); co:outstd_logic; qh:bufferstd_logic_vector(3downto0); ql:bufferstd_logic_vector(3downto0) ); --{{ALTERA_IO_END}}DONOTREMOVETHISLINE! ENDcounter60;--ArchitectureBodyARCHITECTUREcounter_architectureOFcounter60IS BEGINco<='1'when(qh="0101"andql="1001"andci='1')else'0';process(clk,nreset)beginif(nreset='0')thenqh<="0000";ql<="0000";elsifrising_edge(clk)thenif(load='1')thenqh<=d(7downto4);ql<=d(3downto0);elsif(ci='1')thenif(ql=9)thenql<="0000";if(qh=5)thenqh<="0000";elseqh<=qh+1;endif;elseql<=ql+1;endif;endif;endif;endprocess;ENDcounter_architecture;“時(shí)”部分：LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_unsigned.all;--EntityDeclarationENTITYcounter24IS --{{ALTERA_IO_BEGIN}}DONOTREMOVETHISLINE! PORT ( ci:instd_logic; nreset:INSTD_LOGIC:='1'; load:INSTD_LOGIC; clk:INSTD_LOGIC; d:instd_logic_vector(7downto0); co:outstd_logic:='0'; qh:bufferstd_logic_vector(3downto0); ql:bufferstd_logic_vector(3downto0) ); --{{ALTERA_IO_END}}DONOTREMOVETHISLINE! ENDcounter24;--ArchitectureBodyARCHITECTUREcounter_architectureOFcounter24IS BEGIN--co<='1'when(qh="0010"andql="0011"andci='1')else'0';process(clk,nreset)begin--if(nreset='0')then--qh<="0000";--ql<="0000";ifrising_edge(clk)thenif(load='1')thenqh<=d(7downto4);ql<=d(3downto0);elsif(ci='1')then if(qh=0orqh=1)then if(ql=9)then ql<="0000"; if(qh=2)then qh<="0000"; else qh<=qh+1; endif; else ql<=ql+1; endif; else if(ql=3)then ql<="0000"; if(qh=2)then qh<="0000"; else qh<=qh+1; endif; else ql<=ql+1; endif; endif;endif;endif;endprocess; ENDcounter_architecture;3.分頻模塊Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;Useieee.std_logic_arith.all;Entityfdiv_duoisport(clkin:INstd_logic;clkout_200HZ:bufferstd_logic;--鍵盤去抖動(dòng)clkout_1KHZ:bufferstd_logic;--顯示模塊計(jì)數(shù)器clkout_10HZ:bufferstd_logic;--按鍵選擇clkout_1HZ:bufferstd_logic--計(jì)數(shù)器模塊);Endfdiv_duo;Architectureaoffdiv_duoissignalcnt_1HZ:naturalrange0to24999999;signalcnt_10HZ:naturalrange0to249999999;signalcnt_1KHZ:naturalrange0to24999;signalcnt_200HZ:naturalrange0to124999;Beginprocess(clkin)beginif(clkin'eventandclkin='1')thenifcnt_1HZ=24999999thencnt_1HZ<=0;clkout_1HZ<=notclkout_1HZ;elsecnt_1HZ<=cnt_1HZ+1;endif;ifcnt_10HZ=249999999thencnt_10HZ<=0;clkout_10HZ<=notclkout_10HZ;elsecnt_10HZ<=cnt_10HZ+1;endif;ifcnt_1KHZ=24999thencnt_1KHZ<=0;clkout_1KHZ<=notclkout_1KHZ;elsecnt_1KHZ<=cnt_1KHZ+1;endif;ifcnt_200HZ=124999thencnt_200HZ<=0;clkout_200HZ<=notclkout_200HZ;elsecnt_200HZ<=cnt_200HZ+1;endif;endif;endprocess;Enda;4.鍵盤控制模塊時(shí)鐘和分鐘的鍵盤去抖動(dòng)和“增益”，“清零”控制部分：Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;Useieee.std_logic_arith.all;Entitydebounceisport(clk200hz,reset:INstd_logic;--200HZ時(shí)鐘din:INstd_logic;dout:OUTstd_logic);Enddebounce;architectureaofdebounceistypestateis(S0,S1,S2);--定義狀態(tài)機(jī)類型signalcurrent:state;beginprocess(clk200hz,reset,din)beginif(reset='1')then--狀態(tài)機(jī)復(fù)位dout輸出信號(hào)復(fù)位current<=S0;dout<='1';elsif(clk200hz'eventandclk200hz='1')thencasecurrentiswhenS0=>dout<='1';if(din='0')thencurrent<=S1;elsecurrent<=S0;endif;whenS1=>dout<='1';if(din='0')thencurrent<=S2;elsecurrent<=S0;endif;whenS2=>dout<='0';if(din='0')thencurrent<=S2;elsecurrent<=S0;endif;whenothers=>dout<='1';current<=S0;endcase;endif;endprocess;enda;作用解釋：當(dāng)檢測到按鍵被按下時(shí)，將按鍵的輸出直接給計(jì)數(shù)模塊的時(shí)鐘控制通過按鍵控制計(jì)數(shù)時(shí)鐘從而實(shí)現(xiàn)“增益”功能，如果