Basicflow中最終版課件

16四月2024Basicflow中最終版課程目標(biāo)學(xué)完這個(gè)單元后，你應(yīng)該能夠掌握：創(chuàng)建一個(gè)Milkyway庫(kù)來(lái)容納你的設(shè)計(jì)在啟動(dòng)ICCompiler時(shí)會(huì)讀入所有必要的文件,學(xué)會(huì)解決常見的錯(cuò)誤和警告時(shí)序分析和優(yōu)化的設(shè)置能在ICCompiler進(jìn)行布局、時(shí)鐘樹綜合和布線的基本流程UnitRoadmap數(shù)據(jù)建立讀入門級(jí)網(wǎng)表和時(shí)序約束設(shè)置時(shí)序庫(kù)建立Milkyway庫(kù)進(jìn)行平面規(guī)劃基本流程：布局時(shí)鐘樹綜合布線分析建立時(shí)序和RC模型時(shí)序變量RC和TLU+模式延遲計(jì)算GeneralICCompilerFlowSynthesisUnit1Unit3Unit4Unit5Unit6Unit2DesignSetupDesignPlanningplace_optclock_optroute_optChipFinishingICCompiler

布局,CTS,布線及優(yōu)化IPIC

Compiler門級(jí)網(wǎng)表平面規(guī)劃布局、時(shí)鐘樹綜合、布線及優(yōu)化工藝文件TLU+模型IO放置文件(tdf)綜合后網(wǎng)表時(shí)序約束文件SDCIOpads放置Chip/core邊界Cellrows,wiretracks

建立宏單元放置輸出place_optclock_optroute_optChipfinishingandDFMPowerplan標(biāo)準(zhǔn)單元放置創(chuàng)建時(shí)鐘樹完成時(shí)鐘和信號(hào)線布線輸出FloorplanICCompiler數(shù)據(jù)流程DEFMWDesignPlanningUnitFlow:FromSetuptoOutputLogicalDataSetupPhysicalDataSetupplace_optclock_optroute_optAnalysisOutput邏輯數(shù)據(jù)Gate-LevelNetlist(s)LogicalLibraries

.dblinkcheck_timingcreate_clock–period10...

set_input_delay–max1.2...

set_output_delay–max2.5...

set_driving_cell...

Logical(Timing)ConstraintsLogicalDataPhysicalDataplace_optclock_optroute_optAnalysis OutputLogicalData讀入綜合后的門級(jí)網(wǎng)表ICCompiler能夠打開DesignCompiler生成的Milkyway數(shù)據(jù)或是DesignCompiler支持的其它格式可以讀入一個(gè)或多個(gè)文件read_ddcread_verilogread_vhdl…read_verilogfile1.vfile2.v…MilkywayandDDCcanalsocontaindesignattributes!MY_TOP_DESIGN不允許相同的例化名ICCompiler不支持非唯一的設(shè)計(jì)，例如，一個(gè)設(shè)計(jì)的多個(gè)例化具有相同名字！當(dāng)讀入一個(gè)非唯一例化的設(shè)計(jì)，你的ICC腳本的第一個(gè)命令應(yīng)該是:current_designMY_TOP_DESIGNuniquifyPARSERPARSER1PARSER2PARSER3邏輯庫(kù)（.db)為所有標(biāo)準(zhǔn)單元(and,or,flipflop,…)提供時(shí)序和功能信息為硬件宏單元(IP,ROM,RAM,…)提供時(shí)序信息定義驅(qū)動(dòng)/負(fù)載設(shè)計(jì)規(guī)則：最大扇出和跳變最大/最小電容進(jìn)行如下指定：LogicalLibraries

.dbsetlink_library"*gates.dbio.dbrams.db"“*”=Searchalldesignsinmemory要確定所用到的單元包含正確的db!CCSLibrarySupportICCompiler支持NLDM和CCS(CompositeCurrentSource)庫(kù)基于CCS模型具有更加準(zhǔn)確的時(shí)序、噪聲，功耗模型更精確的連線阻抗密勒效應(yīng)動(dòng)態(tài)的IR壓降多電壓閥溫度逆增NLDM模型對(duì)于90納米及以下是不夠精確的，在90納米及以下要用CCS模型CCSSupportedThroughoutGalaxyToolsTimingNoisePowerNanoCharPrimeTimeICCompilerDesignCompilern/aCCSSupportMilkywaySignoffDesignCompilerICCompilerGalaxyICCompiler如何查找文件?默認(rèn)情況下，你必須定義所有文件的路徑（不管是相對(duì)還是絕對(duì)）你可以指定到哪些路徑下尋找文件：以上路徑供ICCompiler用來(lái)讀入或者找到文件lappendsearch_path./design_data../scriptslappendsearch_path[glob$MW_libs/*/LM]目標(biāo)庫(kù)與link_library和search_path變量一樣，你需要定義用于映射和邏輯優(yōu)化的邏輯庫(kù)：默許情況，target_library只指向標(biāo)準(zhǔn)單元庫(kù)settarget_library"gates.db"*邏輯參考庫(kù)門級(jí)網(wǎng)表包含標(biāo)準(zhǔn)單元和宏單元的例化，標(biāo)準(zhǔn)單元和宏單元的時(shí)序信息被存放在邏輯參考庫(kù)里L(fēng)ink命令將確保把所有例化單元的邏輯參考庫(kù)都能找到link

risc_corenandnor

invffsdram_ifGate-LevelNetlist(s)mem.dbgates.dbip.dbpci_corelink_libraryShortcuts…import_designsorca.v\ -formatverilog\ -topORCA_TOPReplaces:read_verilog–netlistorca.vcurrent_designORCA_TOPuniquifylinksave_mw_cel–asORCA_TOPFormatcanbeverilog,db,ddc時(shí)序約束“時(shí)序約束”是用來(lái)把對(duì)設(shè)計(jì)的時(shí)序要求傳達(dá)給ICCompiler應(yīng)與邏輯綜合用的是同一個(gè)時(shí)序約束文件（SDC）create_clock–period10[get_portsclk]

set_input_delay4–clockclk\

[get_portssd_DQ[*]]

set_output_delay5–clockclk

[get_portssd_LD]

set_load0.2[get_portspdevsel_n]

set_driving_cell–lib_cellbuf5\

[get_portspdevsel_n]

...read_sdctiming_constraints.sdcSDC=SynopsysDesignConstraints約束管理remove_sdcRemovesallSDCconstraintsremove_ideal_network-allRemovesideal_networkattributes,latenciesandtransitionsremove_annotationsRemovesallannotateddelays,transition,resistance,capacitance,checksToremoveallsettings:reset_designRemovesalloptimizationattributes(dont_touch,size_only…)andallconstraints.時(shí)序檢查在PR之前，必須確保設(shè)計(jì)是被完全約束的對(duì)于沒有被時(shí)序約束的路徑，ICCompiler將不會(huì)對(duì)其進(jìn)行優(yōu)化對(duì)于缺少外部負(fù)載和驅(qū)動(dòng)特性的約束，不進(jìn)行檢查！check_timing!check_timing報(bào)告所有沒被約束的路徑錯(cuò)誤的路徑同樣被認(rèn)為是沒有被約束的下面命令是用來(lái)驗(yàn)證沒有被約束的路徑是不是OK報(bào)告設(shè)計(jì)中設(shè)置的錯(cuò)誤路徑將這些路徑和check_timing報(bào)告的路徑做比較report_timing_requirementscheck_timing:FalsePathsPhysicalDatacheck_physical_constraintsConstrainedand

linkeddesignPhysical

ReferenceLibraries

(Milkyway)FloorplanIPLogicalDataPhysicalDataplace_optclock_optroute_optAnalysis OutputPhysicalDataPhysicalLibraries包含標(biāo)準(zhǔn)單元和宏模塊布局所必需的物理信息定義布局的unittile單元拼接referencepoint

(typically0,0)Dimension“boundingbox”Pins

(direction,layerandshape)VDDGNDABYNAND_1BlockageSymmetry(X,Y,or90o)FAbstractViewFFBUFINVNORunittile

(site)ReferenceLibraries

(Milkyway)Milkyway參考庫(kù)標(biāo)準(zhǔn)單元信息儲(chǔ)存在“視圖”，例如：CEL:完整的版圖視圖FRAM:用于布局布線的抽象視圖LM:帶時(shí)序和功耗信息的邏輯模型(optional*)CEL/FRAM/and2a1and2a2….xor3a27and2a1and2a2….xor3a27VENDOR_XYZ_std_cell_90nmUsedforP&Rlib_max.dblib_min.db….LM/工藝文件(.tffile)工藝文件對(duì)每一種工藝都是唯一的包含金屬層的技術(shù)參數(shù):每個(gè)金屬層/過(guò)孔的層號(hào)和命名介電常數(shù)每個(gè)金屬層/過(guò)孔的物理和電氣特性每個(gè)金屬層/過(guò)孔的設(shè)計(jì)規(guī)則（最小線寬和最小線間距度等）各種電量的單位和精度要顯示層的顏色和模式…ExampleofaTechnologyFileTechnology{ dielectric =3.7 unitTimeName ="ns" timePrecision =1000 unitLengthName ="micron" lengthPrecision =1000 gridResolution =5 unitVoltageName ="v" }...Layer"m1"{ layerNumber =16 maskName ="metal1" pitch =0.56 defaultWidth =0.23 minWidth =0.23 minSpacing =0.23 ...abc_6m.tf指定參考庫(kù)通過(guò)創(chuàng)建一個(gè)設(shè)計(jì)庫(kù)！怎樣指定物理參考庫(kù)和技術(shù)文件呢？create_mw_libdesign_lib_orca \ -technologytechfile.tf \ -mw_reference_library“scioram32”\ -openNowyouarereadytoapplythefloorplan…ApplyingtheFloorplanRAMSiteArrays

ArrayofplacementsitesCluster

HardBoundaryKeepouts&

PGnetsPortLocations

SignalI/OFixedCellsExample:RAMplacementread_defmy_floorplan.def–allow_physicalAllowsphysical-onlyobjectslikePGnets.CopyingtheFloorplanfromanotherMWCell

如果一個(gè)設(shè)計(jì)已經(jīng)在ICCompilerorJupiterXT平面規(guī)劃過(guò)，再讀入相同設(shè)計(jì)的新網(wǎng)表，這一步是很有用的Cell_ACell_Bcopy_floorplanExistingun-floorplannedcellOpeningaMWDesignfromJupiterXTlappendsearch_path../dbsetlink_library"*gates.dbrams.db"settarget_library"gates.db"open_mw_libmy_jxt_lib.mwopen_mw_celfloorplannedset_tlu_plus_files...;explainedlaterremove_sdcread_sdcmydesign.sdcplace_optclock_optroute_optsave_mw_cel-asroutedApplyyourtimingconstraintsforP&R.檢查物理約束檢查庫(kù)和平面規(guī)劃:物理庫(kù)

邏輯庫(kù)不一致Core中放置單元的面積夠不夠狹窄布局區(qū)域的警告報(bào)告物理單元的數(shù)目、已用的sites和總利用率RC參數(shù)…可以通過(guò)manpage查看更多細(xì)節(jié)check_physical_constraints建立設(shè)計(jì)這一步做完，要保存Milkyway設(shè)計(jì)單元默認(rèn)情況下，link_library,search_path,target_libraryandTLU+settings都會(huì)保存在CEL里如果庫(kù)文件要移到其他地方，必須要重新設(shè)置當(dāng)你重新打開CEL，默認(rèn)情況下儲(chǔ)存的設(shè)置是不會(huì)被用除非這樣設(shè)置:setauto_restore_mw_cel_lib_setuptrueopen_mw_celorca_initsave_mw_cel–asorca_init保存和導(dǎo)入設(shè)計(jì)單元設(shè)計(jì)庫(kù)DesignLibrary

design_lib_orcaTechnologyFile

abc_6m.tfMW

StandardcellsMW

MacrocellsMWPad

cellssc.dbio.dborca_initorca.vorca.sdcorca.defContainerforalldata!link_library

target_library

settingsTLU+RCmodels…morelaterUNIXStructureofaDesignMilkywayDatabase./design_lib_orca/CEL/DatabaseT.O.C,technologydataetc.….…orca_init:1SavedCellMWDesignLibraryliblib_1lib_bckUNIXManipulationofaMilkywayDatabaseUNIX%cdCELUNIX%rmORCA_placedUNIX%cp~Joes_Lib/ORCA_placed.STOP./design_lib_orca/…CEL/ORCA_initORCA_floorplannedORCA_placedORCA_ctsORCA_routedliblib_1lib_bckT.O.C.Corrupted!TestforUnderstandingListthe2variablesthatneedtobesetuptosuccessfullyreadalldesignfiles!Whatisthedifferencebetweenthelink_libraryandthetarget_library?ICCompilerrequiresachip-levelfloorplanincludingIOPADs.True/FalseAfloorplanmustalwaysbeinputtoICCompilerbyreadingaDEFfile.True/FalseWhichofthefollowingisnotrecommended?lappendsearch_pathmy_pathsetsearch_pathmy_pathsetsearch_path"$search_pathmy_path"2Minutes!SummaryGate-LevelNetlistLogicalLibrary

.dbLogicalConstraints

.sdcread_sdcread_defcheck_timing

check_physical_constraintsread_verilog/vhdl/ddcsetlink_library"*sc.db"

settarget_librarysc.dbcreate_mw_lib–technology… –mw_reference_library…IC

CompilerPhysicalConstraints

DEForMWlibraryReadyforPlace&RouteMWReferenceLibraries+techfileOr:import_designICCompilerRecommendedSetup#loadcommonsettings&usefulproceduressource../ref/icc_settings.tcllappendsearch_path./scripts../ref/sdb../ref/dbsetsymbol_library"sc_icon.sdbio_icon.sdb"setlink_library"*sc_max.dbio.dbram16x128_max.db"settarget_library"sc_max.db"create_mw_libdesign_lib_orca-open\

-technologytechfile.tf\

-mw_reference_library"mw/scmw/iomw/ram32"setmw_logic0_net"VSS"setmw_logic1_net"VDD"import_designsdesign.ddc\ -formatddc\ -topORCA_TOPread_def–allow_physicaldesign.defsave_mw_cel–overwrite #CELsavedasORCA_TOPAllsetupdonefirstandstoredin.synopsys_dc.setup.synopsys_dc.setup.synopsys_dc.setup.synopsys_dc.setup$SYNOPSYS/admin/setup~userICCstartupdirectoryUser’sSpecificProjectSetupUser’sGeneralSetupStandardSetupICCompiler3個(gè)初始化文件在.synopsys_dc.setup命令在工具打開時(shí)自動(dòng)導(dǎo)入，導(dǎo)入順序?yàn)?、2、3，且3有最高的優(yōu)先級(jí)213布局階段在布局&優(yōu)化之前:不要對(duì)設(shè)計(jì)單元過(guò)約束約束要符合設(shè)計(jì)規(guī)范布局前先報(bào)告時(shí)序情況采用忽略互聯(lián)線影響來(lái)查找不合實(shí)際和不正確的約束set_zero_interconnect_delay_modetrueWarning:Timerisinzerointerconnectdelaymode.(TIM-177)report_constraint–allreport_timingset_zero_interconnect_delay_modefalseInformation:Timerisnotinzerointerconnectdelaymode.(TIM-176)LogicalDataPhysicalDataplace_optclock_optroute_optAnalysis Outputplace_opt布局和優(yōu)化place_opt反復(fù)執(zhí)行布局和優(yōu)化.

DTDP:布局的首要目標(biāo)是建立時(shí)間slack為正LogicmovedclosertogetherforshorternetsCellsupsizedforoptimaldrive/speed時(shí)鐘樹綜合設(shè)置時(shí)鐘樹綜合時(shí)選項(xiàng)/例外運(yùn)行clock_opt命令創(chuàng)建時(shí)鐘樹執(zhí)行增量的邏輯和布局優(yōu)化運(yùn)行時(shí)鐘樹優(yōu)化對(duì)時(shí)鐘網(wǎng)絡(luò)進(jìn)行布線通過(guò)設(shè)置，clock_opt還能進(jìn)行修復(fù)holdtime違規(guī)執(zhí)行內(nèi)部時(shí)鐘平衡LogicalDataPhysicalDataplace_optclock_optroute_optAnalysis Outputclock_optclock_optRouting布線器進(jìn)行:GlobalRouteTrackAssignmentDetailedRoute 然后執(zhí)行大量的邏輯、布局、布線和串?dāng)_優(yōu)化來(lái)產(chǎn)生最好的布線結(jié)果LogicalDataPhysicalDataplace_optclock_optroute_optAnalysis Outputroute_optroute_opt分析檢查執(zhí)行place_opt和route_opt命令后屏幕輸出的設(shè)計(jì)總結(jié):利用率WNS–WorstNegativeSlackTNS–TotalNegativeSlack單元放置的合法單元數(shù)量和面積設(shè)計(jì)規(guī)則違規(guī)用report_qor命令:每個(gè)路徑組(clockgroup)WNS/TNS其它統(tǒng)計(jì)信息LogicalDataPhysicalDataplace_optclock_optroute_optAnalysis OutputAnalysisAnalysis–Details產(chǎn)生更加詳細(xì)的報(bào)告顯示所有違規(guī)路徑終點(diǎn)report_constraint–all_violators詳細(xì)顯示建立時(shí)間最壞的那條路徑report_timing報(bào)告物理設(shè)計(jì)統(tǒng)計(jì)信息(如.利用率)report_design-physical分析阻塞阻塞圖(GUI)report_congestion采用一致性的名字Imperativewhenexportingdataalways!在Milkyway數(shù)據(jù)庫(kù)中保存設(shè)計(jì)單元保存Verilog網(wǎng)表僅保存平面規(guī)劃信息change_names–hierarchy–rulesverilogsave_mw_cel-asroutedwrite_def-outputfloorplan.defwrite_floorplanfloorplan.tclwrite -formatverilog\

-hierarchy-outputrouted.vOutputLogicalDataPhysicalDataplace_optclock_optroute_optAnalysis OutputOutputExample“run”Scriptlappendsearch_path./design_data../db../tlupsetlink_library"*gates.dbrams.db"settarget_library"gates.db"create_mw_libmy_lib.mw\–technologytech_file.tf\–mw_reference_library"mwlib/gatesmw_lib/rams“\-openimport_designsmy_design.v\ -formatverilog\ -topMYDESIGNset_tlu_plus_files\ -max_tluplusabc_max.tlup\ -min_tluplusabc_min.tlup\ -tech2itf_mapabc.map ;explainedlater…read_sdcmy_design.sdccheck_timingread_def-allow_physicalmy_design.defcheck_physical_constraintsplace_optclock_optroute_optsave_mw_cel-asroutedUNIX$icc_shell–frun.tcl|teemyrun.logrun.tclLocalDiskSpaceUsage在ICCompiler進(jìn)行版圖設(shè)計(jì)流程時(shí),要求足夠的磁盤空間去存儲(chǔ)數(shù)據(jù)，例如:上面表顯示通過(guò)每個(gè)步驟要求的磁盤空間增加，因此完成150K門的設(shè)計(jì),需要56+62+120=238MB.

Designsize

Milkywaydatabase**size(instances)place_optclock_optroute_opt

150K

56MB

62MB

120MB250K

150MB

178MB

303MB400K

242MB

269MB

460MB625K

277MB

325MB

569MB700K

344MB

419MB

741MB850K

917MB

950MB

1.5GB

**thisincludesallCEL/ROUTE/PARA/...viewsplusanyCELattachments靜態(tài)時(shí)序分析ICCompiler的靜態(tài)時(shí)序分析設(shè)置與DesignCompiler、PrimeTime相同用ICCompiler進(jìn)入分析前,需要對(duì)庫(kù)和操作條件設(shè)置.如:setlink_library"*abcmax.db"set_operating_conditions\ –analysis_typeon_chip_variation\ -maxabc_wc-max_libraryabc_max

Usingoperatingconditions‘a(chǎn)bc_wc'foundinlibrary‘a(chǎn)bc_max'.report_timing–delaymax|minMoreComplexSetupinUnit4!時(shí)序優(yōu)化設(shè)置在ICCompiler中，由許多變量和命令來(lái)控制時(shí)序優(yōu)化.例如：setenable_recovery_removal_arcstruesettiming_self_loops_no_skewtrueset_cost_priority{max_delaymax_capacitance}set_ahfs_options-enable_port_punchingtrue記住所有這些變量和命令是很麻煩–用GUI提供幫助!用GUI執(zhí)行時(shí)序優(yōu)化設(shè)置,然后把這些變量和命令拷到設(shè)置文件中時(shí)序優(yōu)化設(shè)置(2/2)基于單元和網(wǎng)絡(luò)計(jì)算時(shí)序延時(shí)ICC為每個(gè)單元和網(wǎng)絡(luò)計(jì)算延時(shí)為計(jì)算延時(shí)，ICC需要知道每個(gè)網(wǎng)絡(luò)的寄生RCCellDelay=

(InputTransitionTime,Cnet+Cpin)NetDelay=

(Rnet,Cnet+Cpin)0.5nsCnetCpinRnetTLU+模型

ICCompiler用網(wǎng)絡(luò)的幾何形狀和TLU+查找表來(lái)計(jì)算CandR超深亞微米加工的效應(yīng)模型SingleProcessFile

(ITF)TLU+ICC,PC,Astro?nxtgrdStar-RCXT?超深亞微米加工效應(yīng)ConformalDielectricMetalFillShallowTrenchIsolationCopperDishing:DensityAnalysisWidth/SpacingTrapezoidConductorSeeAppendixBfordetailsGeneratingTLU+ModelsITF(加工文件)由Foundry廠提供TLU+模型通常是不提供從ITF產(chǎn)生TLU+Where: -itf2TLUPlus generatesTLU+insteadofnxtgrdfile

-i istheITFfile

-o istheoutput,binaryTLU+modelfileunix%grdgenxo-itf2TLUPlus-i<ITFfile>-o<TLU+file>AlwaysusethelatestStar-RCXTreleasetogeneratethemodels.set_tlu_plus_files\ -max_tluplusabc_max.tlup\ -min_tluplusabc_min.tlup\ -tech2itf_mapabc.mapLoadingTLU+ModelsICCompiler檢查search_path去查找TLU+files對(duì)TLU+設(shè)置執(zhí)行一致性檢查確保正確的TLU+和map文件check_tlu_plus_files映射文件映射文件從.tf(MW技術(shù)文件)層/過(guò)孔名映射到Star-RCXT，.itf層/過(guò)孔名。Layer"METAL"{layerNumber =14maskName ="metal1"

…DIELECTRICcm_extra3{THICKNESS=0.06ER=4.2}CONDUCTORcm{THICKNESS=0.26WMIN=0.16…}DIELECTRICdiel1d{THICKNESS=0.435ER=4.2}…abc.itfabc.tfconducting_layers

poly poly

metal1 cm

metal2 cm2

…abc.map計(jì)算單元和網(wǎng)絡(luò)延時(shí)從TLU+模型中可知道網(wǎng)絡(luò)的寄生RC，則可計(jì)算延時(shí)對(duì)于單元延時(shí)，只需要Ctotal/Ceff計(jì)算算法計(jì)算網(wǎng)絡(luò)延時(shí)有：Elmore,ArnoldiC1R1R2R3C3C4U2U1C2預(yù)布線時(shí)的延時(shí)計(jì)算算法布局后布線前，基于虛擬布線來(lái)估計(jì)線長(zhǎng)度由于虛擬布線只是一種估算，用Elmore模型進(jìn)行延時(shí)計(jì)算Pin-to-pintimingVirtualRoute布線后的延時(shí)計(jì)算算法布線后，具體線網(wǎng)已經(jīng)明確，因此抽取更加精確默認(rèn)情況下仍用Elmore模型在后布線計(jì)算時(shí)可打開Arnoldi

模型DetailedRouteBasicFlowSummaryYoushouldnowbeableto:CreateaMilkywaylibrarytoholdyourdesignReadallnecessaryfilesrequiredtorun

ICCompiler,resolvingcommonerrors/warningsSetuptimingforanalysisandoptimizationsExecutethebasicflowforplacement,CTSandroutinginICCompiler45minutesLab1:BaselineflowforICCompilerGoals:SetupdesigndatabaseandtimingPerformbaselineplace,cts&routeoperationswithassociateddefaultoptimizationsCreateMWdatabasewithattachedlibrariesplace_optclock_optroute_optAnalysisandOutputReaddesign,constraints,floorplan設(shè)置設(shè)計(jì)資料庫(kù)課時(shí)間在默認(rèn)的優(yōu)化下執(zhí)行基本操作流程：布局、時(shí)鐘樹綜合和布線操作。AppendixAMW參考庫(kù)的準(zhǔn)備MigrationfromDB/PDBtoMW:TerminologyDC/PCTerminologyMilkywayTerminologyLibraryCompiler(compilelibrary)

read_lib,write_libMilkywaytool(create/edit

MilkywayLibrary)read_lef,read_plib,…Database(db)Librarydb(timing)

PDB(physical)

Designdb/ddcMilkywayLibraryLibrarydb(canbepartof

RefLibasLMview)

ReferenceLibrary

DesignLibrarySetupwithoutusingMilkyway:search_path

link_library

target_librarySetupusingMilkywaylibrary:se