光電子材料導(dǎo)論第一章-信息處理技術(shù)和材料

1、第二章、信息處理技術(shù)和材料,大規(guī)模集成電路為基礎(chǔ)的電子計算機技術(shù)是信息處理的主要技術(shù)，以硅材料為核心的集成電路發(fā)展迅速，它占集成電路的90以上。 1944年馮.諾依曼提出程序存儲和順序計算的概念； 1946年第一臺電子計算機ENIAC誕生； 1948年Bell Lab發(fā)明了二極管；1954年第一臺晶體管計算機誕生；1958年Firchrd公司的諾宜斯發(fā)明了第一塊集成電路， 1968年摩爾、諾宜斯和管理能手格羅夫創(chuàng)立Intel公司，Intel成為現(xiàn)代計算機的主流。, 課件下載地址,半導(dǎo)體動態(tài)隨機存儲器,自1958年問世以來，硅集成電路器件集成度提高了100 萬倍，單位價格下降為100萬分之一。這

2、主要與光刻線寬縮小和成品率提高、單晶硅片的尺寸增大和質(zhì)量提高有關(guān)。 目前，大規(guī)模硅集成電路以MOS（Metal On Silicon）為主流技術(shù)，迎來深亞微米（0.1 m）硅微電子技術(shù)。器件最小溝道長度將縮小到 30 nm 50 nm，柵氧化層厚度為 2 nm，需要考慮諸如：強場效應(yīng)、絕緣氧化物量子隧穿、溝道摻雜原子統(tǒng)計漲落、互聯(lián)時間常數(shù)與功耗和光刻技術(shù)等。 小于0.1 m 的線條屬于納米范疇，它的線寬已與電子的德布羅意數(shù)相近。電子在此種器件內(nèi)部的輸運和散射會呈現(xiàn)量子化特性。,固態(tài)納米電子器件可按照電子在固體中受限的具體情況分為三類，即量子點器件（人造原子）、共振隧穿器件（共振隧穿二極管RTD

3、S和振隧穿晶體管RTTS）以及庫侖阻塞效應(yīng)的單電子器件（單電子晶體管SET”S和單電子存儲器SEMS）。納米電子器件的一個共同特征是它們都有一個尺寸在5 nm 100 nm 之間的由半導(dǎo)體或金屬材料組成的“小島”，行為類似于FET器件的溝道，“島”被勢壘所包圍，以阻止電子進入島區(qū)。 制作固體量子器件采用IIIV 族化合物半導(dǎo)體材料（易獲得高晶體質(zhì)量和原子級平滑界面的異質(zhì)結(jié)構(gòu)材料和高的電子遷移率）。但缺乏理想的絕緣介質(zhì)和頂層表面暴露于大氣而導(dǎo)致的氧化或雜質(zhì)污染等，人們把目光投向發(fā)展硅基材料體系。,1998 年出現(xiàn)了絕緣層上硅材料SOI（Silicon On Insulator），它推動微電子技術(shù)

4、的進一步發(fā)展。與硅基材料及其器件相比，由于避免了器件與襯底間的寄生效應(yīng)，SOI具有許多優(yōu)點。如，高的開關(guān)速度、高密度、抗輻射、無閉鎖效應(yīng)等，與CMOS技術(shù)相比，SOI技術(shù)使芯片的性能提高35。,當(dāng)計算機浮點運算速度高于100億次以上時，需要考慮光信息處理。 光信息處理可以充分發(fā)揮并列處理的優(yōu)點，能高速處理信號。以圖像為對象的光信息處理已研究多年。 目前，以全光計算機為目標(biāo)的、用光學(xué)系統(tǒng)完成一維或多維數(shù)據(jù)的數(shù)字計算還處于探索階段。 研制出高效低功耗的光子器件及相應(yīng)的材料仍然是關(guān)鍵所在。在并列處理中首先要有面陣的光子集成器件。 高密度垂直腔面發(fā)射激光器（VCSEL）的光子集成回路是二維光信息實時處

5、理和圖形識別的關(guān)鍵器件。 目前研制出的高密度對稱反射式自電光效應(yīng)（SRSEED）無腔面的光雙穩(wěn)態(tài)開關(guān)集成面陣，可在光功耗極低（小于10 fJ/m2）情況下對光信息進行多路和二維處理。,電子計算機電路中的電阻和電容使電信號的傳遞速度受到RC馳豫時間的限制，并產(chǎn)生“時鐘歪斜”、互聯(lián)擁擠、電子信號容易自身干擾等問題， 光互聯(lián)集成回路可以解決這個問題。若干個光學(xué)開關(guān)和存儲器以及光電轉(zhuǎn)換元件用波導(dǎo)方式連成回路，這時的信息處理器是光電混合型的。 通過發(fā)展可尋址的光源陣列、光學(xué)雙穩(wěn)態(tài)門陣列、全息衍射光柵和監(jiān)測器陣列，并行通道可達106數(shù)量級。進一步發(fā)展光學(xué)神經(jīng)網(wǎng)絡(luò)、光計算算法和結(jié)構(gòu)及高密度交叉光互聯(lián)等技術(shù)逐

6、步發(fā)展成全光計算機。,需要發(fā)展光信號處理技術(shù)及材料,All-optical signal processing,Wavelength conversion All-optical logic gates Optical Add/Drop Multiplexing (OADM) 3 R regeneration Optical sampling All-optical demultiplexing All-optical packet switching,半導(dǎo)體材料（半導(dǎo)體激光器和放大器） 材料特點 非線性系數(shù)大（僅需要毫瓦量級的功率） 響應(yīng)速度快（可實現(xiàn)百皮秒、皮秒及飛秒） 體積小重量輕（易于

7、集成） 缺點 偏振相關(guān) 碼型相關(guān),Outline,Introduction Review of Fabry-Perot laser diode properties All-optical header processor All-optical packet switch All-optical add/drop node Conclusion,All-optical packet switching,The concept of the packet,Packet-switched networks will be the networks of the future,Payload,He

8、ader,Guard Period,All-Optical or Hybrid-Optical Packet Switching,Hybrid optical packet switching The packet headers are converted into the electrical domain for processing The data payload remains in the optical domain Advantage Combines the processing power of electronics and the transmission bandw

9、idth of optical fibers Disadvantage Processing speed limited by electronics and the required optical to electrical and electrical to optical conversions,All-Optical Packet Switching,Both the header processing and packet forwarding/switching are carried out in the optical domain Advantages Ultra-high

10、 speed operation by eliminating the optical-electrical and electrical-optical conversion Cost reduction Difficulties Lack of optical random access memory Lack of sophisticated all-optical processing power,All-Optical Packet Switching Requires,All-optical signal processing to read the packet headers

11、Only simple bit-wise optical logic gates have been demonstrated All-optical memory so that the decision made by the header processor can affect the entire packet Optical flip-flops are demonstrated H. J. S. Dorren et al., J. Lightwave Technol., 21, 2 (2003). M. Takenaka and Y. Nakano, Proc. OFC 2004

12、, paper WL4. All-optical packet forwarding/routing e.g., on/off switches,Outline,Introduction Review of Fabry-Perot laser diode properties All-optical header processor All-optical packet switch All-optical add/drop node Conclusion,Injection Locking: Overview,First proposed by Van der Pol in 1927 “Fo

13、rced oscillations in a circuit with a negative resistance,”Phil. Mag. Series 73, 65 (1927).,Injection locking of FP-LD (Fabry Perot Laser Diode) Injected l should fall within injection locking range of FP modes Minimum injection power & polarization matching required Red-shift of mode comb after inj

14、ection locking asymmetric injection locking curve (Roy Lang, IEEE JQE 82),Review of the Properties of FP-LD,Single-mode injection locking:,Input Power (dB),Output Power (dB),lc,(i) without ld,FP- LD spectrum,l source,FP-LD,Spectra of Free-Running and Injection-Locked FP-LD,Experimental Setup,OSA,PC,

15、CIR,( PC = Polarization Controller ),( CIR = Circulator ),Review of the Properties of FP-LD,Multi-mode injection locking: the presence of a signal at ld affects lowers the injection locking threshold of the signal at lc,Input Power (dB),Output Power (dB),lc,(ii) with ld,FP- LD spectrum,ld,Review of

16、the Properties of FP-LD,Bistability: it takes less power to sustain injection locking than initiating one,Input Power (dB),lc,(ii) with ld,FP- LD spectrum,ld,Review of the Properties of FP-LD,Mode-shift induced by injection locking the gain at data wavelength ld is affected by the presence of a sign

17、al at lc,L. Y. Chan et al., Opt. Lett., 28, 837 (2003).,Injection Locking Depends on:,Polarization of the input signal in FP-LD Optical input power into the FP-LD Wavelength Detune,Outline,Introduction Review of Fabry-Perot laser diode properties All-optical header processor All-optical packet switc

18、h All-optical add/drop node Conclusion,A novel two-level control signal,Operation Principle,Input control packet (lc),b. Input data packet (ld),Payload,Header,Pth1,Pth2,Pth3,Output control packet (lc),PH,PT,PH,PT,Operation Principle,Output control packet (lc),Input control packet (lc),b. Input data

19、packet (ld),Injection-locked,L. Y. Chan, et al. “All-optical header processing by using an injection-locked Fabry-Perot laser diode,” (to appear in February 2005 issue of Microwave and Optical Technology Letters.),Experimental Setup,Experimental Details,Data Packets The header rate is 5 Gb/s and the

20、 payload rate is 10 Gb/s 2 packets with same data pattern but different header Total packet length is 64 bits (at 10 Gb/s) Guard band: 10 bits Input signal wavelengths, power and detune: Data: 1533.69 nm, -20.35 dBm, +0.03 nm, Control: 1539.38 nm, -1.83 dBm, +0.16 nm, CW: 1536.47 nm, -11.95 dBm, +0.

21、03 nm FP-LD Double-channel planar-buried InGaAsP heterostructure. Driving current : 13 mA Temperature: 15 C,Experimental Input Signals,Header at 5 Gb/s payload at 10 Gb/s,Data Packets 1,Control Packets,Data Packets 2,500 ps / div,Header,Payload,Experimental Results,Header at 5 Gb/s payload at 10 Gb/

22、s,data packets,INPUT,control signal,OUTPUT,2 ns/div,pk_1,pk_2,ON,OFF,switched control signal,Using a single Fabry-Perot laser diode,Review of the Properties of FP-LD,Mode-shift induced by injection locking the gain at data wavelength ld is affected by the presence of a signal at lc,L. Y. Chan et al.

23、, Opt. Lett., 28, 837 (2003).,Operation Principle,Output control packet (lc),Input control packet (lc),b. Input data packet (ld),Payload,Header,Guard Period,Injection-locked,Not Injection-locked,Operation Principle,Output control packet (lc),Input control packet (lc),b. Input data packet (ld),d. Out

24、put data packet (ld),Data Packet Blocked,Data Packet Transmitted,Payload,Header,Guard Period,Injection-locked,Not Injection-locked,Proposed 1N All-Optical Packet Switch,output port N (address = 001),output port 1 (address = 100),output port 2 (address = 010),PP,PP,PP,N bits,coupler,implements a nove

25、l self-routing address protocol that requires only bitwise processing X. C. Yuan, V O. K. Li, C. Y. Li, and P. K. A. Wai, “A novel self-routing scheme for all-optical packet switched networks with arbitrary topologies,” J. Lightwave Technol., vol. 21, pp. 329-339 (2003),_,Proposed 1N All-Optical Pac

26、ket Switch,output port N (address = 001),output port 1 (address = 100),output port 2 (address = 010),coupler,_,PP,PP,PP,Data packet format,Proposed 1N All-Optical Packet Switch,output port N (address = 001),output port 1 (address = 100),output port 2 (address = 010),coupler,_,PP,PP,PP,Data packet fo

27、rmat,Proposed 1N All-Optical Packet Switch,output port N (address = 001),output port 1 (address = 100),output port 2 (address = 010),coupler,_,PP,PP,PP,Data packet format,Proposed 1N All-Optical Packet Switch,output port N (address = 001),output port 1 (address = 100),output port 2 (address = 010),c

28、oupler,_,PP,PP,PP,Data packet format,Proposed 1N All-Optical Packet Switch,output port N (address = 001),output port 1 (address = 100),output port 2 (address = 010),coupler,_,PP,PP,PP,Data packet format,Experimental Setup,P. K. A. Wai, et al., CLEO2004, paper CTuFF2.,Experimental Details,Data Packet

29、s The header rate is 5 Gb/sand the payload rate is 10 Gb/s 4 packets with same data pattern but different headers Total packet length is 64 bits (at 10 Gb/s) Guard band: 10 bits Input signal wavelengths, power and detune: Data: 1535.21 nm, -15 dBm, +0.08 nm, Control: 1539.99 nm, +0.17 dBm, -1.04 nm,

30、 CW: 1537.02 nm, -8.50 dBm, +0.02 nm FP-LD Double-channel planar-buried InGaAsP heterostructure. Driving current : 13.5 mA Temperature: 15 C,data packets control signals data packet headers control signal headers switched data packets zoom-in switched data packets,Experimental Results,Separate heade

31、r processing and packet switching,Two-stage Switching,Local Control Signal,d,AOHP,AOS,c,Two-stage Switching,Local Control Signal,AOHP,AOS,Two-stage Switching,AOHP,AOS,Two-stage Switching,AOHP,AOS,Two-stage Switching,AOHP,AOS,Two-stage Switching,AOHP,AOS,Two-stage Switching,AOHP,AOS,Two-stage Switchi

32、ng,AOHP,AOS,Experimental Setup,control signal,data signal,CW signal,AOS,AOHP,FP-LD,SOA,Experimental Details,Data Packets The header rate is 5 Gb/sand the payload rate is 10 Gb/s 4 packets with same data pattern but different headers Total packet length is 64 bits (at 10 Gb/s) Guard band: 10 bits Inp

33、ut signal wavelengths, power and detune: Data: 1542.76 nm, -6.9 dBm, +0.01 nm, Control: 1540.16 nm, -5.9 dBm, +0.22 nm, CW: 1537.13 nm, -11 dBm, +0.02 nm FP-LD Double-channel planar-buried InGaAsP heterostructure. Driving current : 2 threshold current Temperature: 15 C,Experimental Results,data pack

34、ets,control signals,data packet headers,control signal headers,switched control signals,switched control signals,switched data packets,zoom-in switched control signals,data packets,Experimental Results,Experimental Results,switched control signals,switched data packets,zoom-in switched control signa

35、ls,data packets,Outline,Introduction Review of Fabry-Perot laser diode properties All-optical header processor All-optical packet switch All-optical add/drop node Conclusion,All-optical add/drop node for an all-optical packet-switched ring network,All-Optical Add/Drop Node,Local Control Signal,d,AOH

36、P,ADD PORT,DROP PORT,AOS-1,AOS-2,d,c,Inverter,TRANSIT PORT,RING NETWORK,All-Optical Add/Drop Node,Local Control Signal,AOHP,ADD PORT,DROP PORT,AOS-1,AOS-2,Inverter,TRANSIT PORT,RING NETWORK,All-Optical Add/Drop Node,AOHP,ADD PORT,DROP PORT,AOS-1,AOS-2,Inverter,TRANSIT PORT,RING NETWORK,All-Optical A

37、dd/Drop Node,AOHP,ADD PORT,DROP PORT,AOS-1,AOS-2,Inverter,TRANSIT PORT,RING NETWORK,All-Optical Add/Drop Node,AOHP,ADD PORT,DROP PORT,AOS-1,AOS-2,Inverter,TRANSIT PORT,RING NETWORK,All-Optical Add/Drop Node,AOHP,ADD PORT,DROP PORT,AOS-1,AOS-2,Inverter,TRANSIT PORT,RING NETWORK,All-Optical Add/Drop N

38、ode,AOHP,ADD PORT,DROP PORT,AOS-1,AOS-2,Inverter,TRANSIT PORT,RING NETWORK,All-Optical Add/Drop Node,Local Control Signal,AOHP,ADD PORT,DROP PORT,AOS-1,AOS-2,Inverter,TRANSIT PORT,RING NETWORK,All-Optical Add/Drop Node,AOHP,ADD PORT,DROP PORT,AOS-1,AOS-2,Inverter,TRANSIT PORT,RING NETWORK,All-Optica

39、l Add/Drop Node,AOHP,ADD PORT,DROP PORT,AOS-1,AOS-2,Inverter,TRANSIT PORT,RING NETWORK,All-Optical Add/Drop Node,AOHP,ADD PORT,DROP PORT,AOS-1,AOS-2,Inverter,TRANSIT PORT,RING NETWORK,All-Optical Add/Drop Node,AOHP,ADD PORT,DROP PORT,AOS-1,AOS-2,Inverter,TRANSIT PORT,RING NETWORK,All-Optical Add/Dro

40、p Node,AOHP,ADD PORT,DROP PORT,AOS-1,AOS-2,Inverter,TRANSIT PORT,RING NETWORK,All-Optical Add/Drop Node,Local Control Signal,d,AOHP,ADD PORT,DROP PORT,AOS-1,AOS-2,d,d,c,Inverter,RING NETWORK,TRANSIT PORT,Experimental Results,input data packets,input locked control packet for added port,added data pa

41、cket,input control signal for transmitted port,transmitted data packet,data packets at the node output,Design of an All-Optical Packet-Switched Ring Network,Slotted networks The addresses of empty packets are encoded such that they will be accepted by every node. Each node will continue to transmit

42、empty packets even if they have nothing to send If a local packet is blocked at the add port, a signal will be sent back to a electronic controller to resend the packet into the ring,Discussions,The wavelength and power tolerance for the control signal are about 0.05 nm and 1 dB The wavelength and power tolerance for the data packets are about 0.02 nm and 3 dB respectively The switching ratio is about 7.5 dB measured in the time domain with zero level at around 20 dBm The loc