PI6C185-02B中文資料

1、PI6C185-02B中文資料PI6C185-02BPrecision 1-7 Clock BufferPin Configuration123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567

2、8901212345678901234567890123456789012123456789012Block DiagramFeaturesHigh speed: 140 MHzLow noise non-inverting 1-7 buffer Supports up to three SDRAM DIMMsLow skew (16-pin TSSOP (L) and QSOP (Q) packagesDescriptionThe PI6C185-02B, a high-speed low-noise 1-7 non-inverting buffer, is designed for SDR

3、AM clock buffer applications. It is intended to be used with the PI6C10X clock generator for Intel Architecture-based Mobile systems.At power up, all SDRAM outputs are enabled and active. The I 2C Serial control may be used to individually activate/deactivate any of the seven output drivers.Note:Pur

4、chase of I 2C components from Pericom conveys a license to use them in an I 2C system as defined by Philips.123Vss 4BUF_IN 5SDRAM16Vdd 7SCLK8SDRAM2SDRAM6Vss VddSDRAM3Vss SDATA161514131211109Vdd SDRAM0SDRAM4SDRAM516-Pin L,Q123456789012345678901234567890121234567890123456789012345678901212345678901234

5、56789012345678901212345678901234567890123456789012123456789012Precision 1-7 Clock BufferPin DescriptionPI6C185-02 Serial Configuration MapByte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable)Note: Inactive means outputs are held LOWand are disabledfrom switchingPI6C185-02B I 2C Address Ass

6、ignment6A 5A 4A 3A 2A 1A 0A W /R 11 1 1 t i B #n i P no i t p i r c s e D 7t i B 62M A R D S 6t i B -)0o t e z i l a i t i n I (C N 5t i B -)0o t e z i l a i t i n I (C N 4t i B -)0o t e z i l a i t i n I (C N 3t i B 31M A R D S 2t i B 20M A R D S 1t i B -)0o t e z i l a i t i n I (C N 0t i B -)0o t

7、 e z i l a i t i n I (C N Byte1: SDRAM Active/Inactive Register (1 = enable, 0 = disable)t i B #n i P no i t p i r c s e D 7t i B 616M A R D S 6t i B 515M A R D S 5t i B -)0o t e z i l a i t i n I (C N 4t i B -)0o t e z i l a i t i n I (C N 3t i B 214M A R D S 2t i B 113M A R D S 1t i B -)0o t e z i

8、 l a i t i n I (C N 0t i B -)0o t e z i l a i t i n I (C N n i P l a n g i S e p y T .y t Q no i t p i r c s e D 61,51,21,11,6,3,26.0M A R D S I 7s t u p t u O k c o l C d e r e f f u B 5N I _F U B I 1t u p n I r e f f u B k c o l C 8A T A D S O /I 1I r o f a t a D l a i r e S 2e c a f r e t n i C 9

9、K L C S I 1I r o f k c o l C l a i r e S 2e c a f r e t n i C 31,7,1V D D r e w o P 3y l p p u S r e w o P V 3.341,01,4V SS dn u o r G 3dn u o r G12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012Precision 1-7

10、Clock Bufferl o b m y S r e t e m a r a P no i t i d n o C t s e T .n i M .p y T .x a M st i n U I D D t n e r r u C y l p p u S z H M 0=N I _F U B 3A m I D D t n e r r u C y l p p u S z H M 66.66=N I _F U B DB T I DD tn e r r u C y l p p u S zH M 0.001=N I _F U B The I 2C interface permits individu

11、al enable/disable of each clock output and test mode enable.The PI6C185-02B, a slave receiver device, cannot be read back.Sub addressing is not supported. To change one of the control bytes, all preceding bytes must be sent.Every byte put on the SDATA line must be 8-bits long (MSB first),followed by

12、 an acknowledge bit generated by the receiving device.During normal data transfers, SDATA changes only when SCLK is LOW. Exceptions: A HIGH to LOW transition on SDATA while SCLK is HIGH indicates a “start” condition; a LOW to HIGH transition on SDATA while SCLK is HIGH is a “stop” condition and indi

13、cates the end of a data transfer cycle.Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW = write to addressed device). If

14、the devices own address is detected, PI6C185-02B generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected.Following acknowledgement of the address byte (0D2H), two more bytes must be sent:1. “

15、Command Code” byte &2. “Byte Count” byte.Although the data bits on these two bytes are “dont care,” they must be sent and acknowledged.2-Wire I 2C ControlStorage Temperature .65C to +150C Ambient Temperature with Power Applied.0C to +70C 3.3V Supply Voltage to Ground Potential .0.5V to +4.6VDC Input

16、 Voltage .0.5V to +4.6V Note:Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress ratingonly and functional operation of the device at these or any otherconditions above those indicated in the operational sections ofthis specification is

17、 not implied. Exposure to absolute maximumrating conditions for extended periods may affect reliability.Supply Current (V DD = +3.465V, Cload = max)Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)1234567890123456789012345678901212345678901234567890123456

18、7890121234567890123456789012345678901212345678901234567890123456789012123456789012Precision 1-7 Clock BufferSDRAM Clock Buffer Operating SpecificationAC TimingDC Operating Specifications (V DD = +3.3V 5%, T A = 0C 70C)l o b m y S r e t e m a r a P n o i t i d n o C .n i M .p y T .x a M s t i n U I N

19、 I M H O t n e r r u c p u -l l u P V T U O V 0.2=04 Am I X A M H O t n e r r u c p u -l l u P V T U O V 531.3=63I N I M L O t n e r r u c n w o d -l l u P V T U O V 0.1=04I X A M L O t n e r r u c n w o d -l l u P V T U O V 4.0=83t H R M A R D S e t a r e g d e e s i r t u p t u O y l n o M A R D S

20、 %5V 3.3V 4.2-V 4.05.14sn /V t H F MA R D S e t a r e g d e l l a f t u p t u O yl n o M A R D S %5V 3.3V4.0-V 4.25.14l o b m y S re t e m a r a P no i t i d n o C .n i M .x a M st i n U e g a t l o V t u p n I V H I e g a t l o V h g i H t u p n I V DD 0.2V D D 3.0+V V L I e g a t l o V w o L t u p

21、 n I V S S 3.0 8.0I LI tn e r r u C e g a k a e L t u p n I V D 5-5+AV D D %5V 3.3=V H O e g a t l o V h g i H t u p t u O I H O A m 1 =4.2VV LO eg a t l o V w o L t u p t u O I L O Am 1=4.0C N I e c n a t i c a p a C n i P t u p n I 5F p C T U O e c n a t i c a p a C s n i p t u p t u O 6L N I P e

22、c n a t c u d n I n i P 7H n T Aer u t a r e p m e T t n e i b m A wo l f r i A o N 0 7Col o b m y S re t e m a r a P z H M 66z H M 001z H M 331st i n U .n i M .x a M .n i M .x a M .n i M .x a M t P K D S d o i r e p K L C M A R D S 0.515.510.015.015.78.7sn t H K D S e m i t h g i h K L C M A R D S

23、6.53.30.1t L K D S e m i t w o l K L C M A R D S 3.51.30.1t E S I R D S e m i t e s i r K L C M A R D S 5.10.45.10.45.10.4sn /V t L L A F D S e m i t l l a f K L C M A R D S 5.10.45.10.45.10.4t H L P y a l e d p o r p H L r e f f u B M A R D S 0.15.50.15.50.15.5sn t L H P y a l e d p o r p L H r e f

24、 f u B M A R D S 0.15.50.15.50.15.5t L Z P t ,H Z P y a l e d e l b a n E r e f f u B M A R D S 0.10.80.10.80.10.8t Z L P t ,Z H P y a l e d e l b a s i D r e f f u B M A R D S 0.10.80.10.80.10.8e l c y C y t u D V5.1t a d e r u s a e M 545554555455%t WK S D S we k S t u p t u O o t t u p t u O M A

25、R D S 052052052sp12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012Precision 1-7 Clock BufferFigure 1. Clock WaveformsNotes:1.Maximum rise/fall times are guaranteed at maximum specified load.2.Minimum rise/fall

26、 times are guaranteed at minimum specified load.3.Rise/fall times are specified with pure capacitive load as shown.Testing is done with an additional 500? resistor in parallel.Minimum and Maximum Expected Capacitive LoadsDesign Guidelines to Reduce EMI1.Place R S series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. R S Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specifie