VHDL程序設(shè)計(jì)題

1、VHDL程序設(shè)計(jì)題四、編程題（共50分）1、請補(bǔ)全以下二選一VHDL程序(本題10分)En tity mux isport(dO,d1,sel:in bit;q:out BIT );(2)end mux;architecture connect of MUX issig nal tmp1,TMP2,tmp3:bit;begincale:blockbegintmp1=d0 and sel;tmp2=d1 and (not sel)tmp3= tmp1 and tmp2;q=tmp3;(8)end block cale;(10)end CONNECT2、編寫一個(gè) 2 輸入與門的 VHDL 程序，請

2、寫出庫、程序包、實(shí)體、構(gòu)造體相關(guān)語句，將 端口定義為標(biāo)準(zhǔn)邏輯型數(shù)據(jù)結(jié)構(gòu)（本題 10 分）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;（ 2）ENTITY nand2 ISPORT （a， b:INSTD_LOGIC;（4）y:OUT STD_LOGIC）;（ 6）END nand2;ARCHITECTURE nand2_1 OF nand2 IS（ 8）BEGINy = a NAND b; -與 y =NOT（ a AND b）; 等價(jià)（10）END nand2_1;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTI

3、TY decoder_3_to_8 ISPORT (a,b,c,g1,g2a,g2b:IN STD_LOGIC;y:OUT STD_L0GIC_VECT0R(7 DOWNTO 0):(2)END decoder_3_to_8;ARCHITECTURE rtl OF decoder_3_to_8 ISSIGNAL indata:STD_LOGIC_VECTOR (2 DOWNTO 0);( 4)BEGINin data y y y y y y y y y = XXXXXXXX;END CASE;ELSEy = 11111111;(14)END IF;END PROCESS;(16)END rtl

4、;（本題14分）魅抿輸人控劇塌扎數(shù)據(jù)諭岀dinendoutX 102001 111.表7-5三態(tài)門真范袤圖了-畀2總門電圖LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY tri_gate ISP0RT(di n,e n:IN STD_LOGIC;dout : OUT STD_LOGIC);ARCHITECTURE zas OF tri_gate ISBEGINPROCESS (di n,e n)BEGINIF (en= 1) THEN dout = din;ELSEdout = Z END IF;END PROCESS ;END zas ;8 分

5、)四、編程題（共50分）1、根據(jù)一下四選一程序的結(jié)構(gòu)體部分，完成實(shí)體程序部分（本題en tity MUX4 isport(s:instd_logic_vector(1dow nto0);(4)d:instd_logic_vector(3dow nto0);(6)y:out std_logic(8)工end MUX4;architecture behave of MUX4 isbeginprocess(s)beginif (s=00) then y=d(0);elsif (s=01) then y=d(1);elsif (s=10) then y=d(2);elsif (s=11) then y

6、=d(3);elsenull;end if;end process;end behave;，要求使能信號 g 低電1 。（本題 10 分）2、編寫一個(gè)數(shù)值比較器 VHDL 程序的進(jìn)程 （不必寫整個(gè)結(jié)構(gòu)框架） 平時(shí)比較器開始工作，輸入信號p = q，輸出equ為 0否則為(2)process(p,q)beginif p = q the nequ = O;(6)elseequ = 1;(8)end if;elseequ = 1;(10)end if;end process;3、填寫完成一個(gè)8-3線編碼器的VHDL程序(16分)。Library ieee;use ieee.std_lo gic_11

7、64.all;use ieee.std_logic_arith.all;use ieee.std_logic_ un sig ned.all;en tity eight_tri is(2)port(b:in stdo gic_vector(7 dow nto 0);en: in std_logic;y:out std_logic_vector(2 downto 0)(4)；end eight_tri;architecture a of eight_tri is(6)sig nal sel: std_logic_vector(8 dow nto 0);beginsel=en & b;(8)y=“

8、 000” when (sel= ” 100000001 ” )else001” when (sel= ” 100000010 ” )else(10)“ 010”when(sel=”100000100”)else“ 011”when(sel=”100001000”)else“100” when (sel=)00f0000” )else(12)“101”when(sel=”100100000”)else110” when (sel= ” 101000000 ” )else(14)“111” when (se1=0000000” )else(16)a ?zzz ；4、圖中給出了 4位逐位進(jìn)位全加器

9、，請完成其 VHDL程序。（本題16分）library IEEE;use lEEE.stdogic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_ un sig ned.all;en tity full_add isport (a,b:in std logic vector (3 downto 0)(2)carr:inout std_logic_vector (4 dow nto 0);sum:out std_logic_vector (3 downto 0)architecture full_add_arch of full

10、_add is component adderport (a,b,c:instd_logic;(6)carr:inout std_logic;sum:outstd_logic);end comp onent;begincarr(0)=0：u0:adder port map(a(0),b(0),carr(0),carr(1),sum(0);u1:adder port map(a(1),b(1),carr(1),carr(2),sum(1);(8) (10)u2:adder port map(a(2),b(2),carr(2),carr(3),sum(2);(12)u3:adder port ma

11、p(a(3),b(3),carr(3),carr(4),sum(3);(14) (16)end full_add_arch;四、編程（共50分）library IEEE;use lEEE.stdogic_1164.all;en tity VposDff isport (CLK, CLR, D: inSTD_LOGIC:2 分Q, QN: out STD_LOGIC ):4 分end VposDff： architecture VposDff_arch of VposDff isbeginprocess ( CLK, CLR )6 分beginif CLR=1 the nQ = O： QN =1

12、：elsif CLKeve nt and CLK=1 the nQ = D: QN = not D:8 分end if：end process：10 分2、完成以下 4 位全加器代碼（本題 10 分）library IEEE;use IEEE.std_logic_1164.all;entity full_add isport (a,b:instd_logic_vector (3 downto 0);cin:instd_logic;cout:out std_logic;sum:outstd_logic_vector (3 downto 0);end full_add;architecture f

13、ull_add_arch of full_add iscomponent adderport (a,b,c:instd_logic;carr:outstd_logic;sum:outstd_logicend comp onent;sig nal c1,c2,c3: std logic;beginu0:adderport map(a(0),b(0),ci n,c1,sum(0);u1:adderport map(a(1),b(1),c1,c2,sum(1):u2:adderport map(a(2),b(2),c2,c3,sum(2):u3:adderport map(a(3),b(3),c3,

14、cout,sum(3):10分end full_add_arch;3、補(bǔ)充完整如下代碼，使之完成4狀態(tài)不斷循環(huán)。（本題10分）ARCHITECTURE arc OF ss IStype states is ( st0,st1,st2,st3);sig nal outc: states:BEGINPROCESS(clk)BEGINIF reset=1 thenoutc outc outc outc outc outc =stO;END CASE;end if;END PROCESS;END arc;4、設(shè)計(jì)異或門邏輯：（本題20分）如下異或門，填寫右邊的真值表。（此項(xiàng)5 分）ABY000其表達(dá)式

15、可以表示為:（此項(xiàng)5分）這一關(guān)系圖示如下:（此項(xiàng)10 分）試編寫完整的VHDL代碼實(shí)現(xiàn)以上邏輯。可以采用任何描述法。library ieee;use ieee.std_logic_1164.all;en tity yihuol isport( a,b :in std_logic;y :out std_logic );end yihuol;architecture yihuo1_behavior of yihuol isbeginprocess(a,b)y：:a x(r b;begin(第2種寫法）if a=b the ny=0;elsey=1;end if;end process;10分end

16、 yihuo1_behavior;四、 編程（共 50 分，除特殊聲明，實(shí)體可只寫出 PORT 語句，結(jié)構(gòu)體要寫完整）1、用IF語句編寫一個(gè)二選一電路，要求輸入a、b, sei為選擇端，輸出q。(本題10分)Entity sel2 isPort (a,b : in std_iogic;sei : in std_iogic;q : out std_iogic);End sei2;(3)Architecture a of sei2 isbeginif sei = 0thenq = a;(6)eiseq = b;(9)end if;2、編寫一個(gè)4位加法計(jì)數(shù)器 VHDL程序的進(jìn)程（不必寫整個(gè)結(jié)構(gòu)框架）

17、，要求復(fù)位信號reset低電平時(shí)計(jì)數(shù)器清零，變高后，在上升沿開始工作；輸入時(shí)鐘信號為elk，輸出為q。（本題10分）Process(reset,clk)(2)beginif reset = 0 the nq = 0000 ”；(4)elsif elk event and clk = 1 then (6)q = q + 1；(9)end if;end process;(10)3、填寫完成一個(gè)8-3線編碼器的真值表（5分），并寫出其VHDL程序（10分）。8 -3線編碼器真值表enby0y1y21000000000001000000100011000001000101000010000111000

18、100001001001000001011010000001101100000001110xxxxxxxx高阻態(tài)en tity eight_tri isport(b:in stdo gic_vector(7 dow nto 0);en: in std_logic;y:out std_logic_vector(2 downto 0);end eight_tri;(3) architecture a of eight_tri issig nal sel: std_logic_vector(8 dow nto 0);(4)beginsel=e n & b;y=“ 000 ” when (sel=10

19、0000001 ” )else001”when (sel=100000010 ”)else010”when (sel=100000100 ”)else011”wh(esnel= ”100001000 ” )else100”when (sel=100010000 ”)else101”when (sel=100100000 ”)else110”when (sel=101000000 ”)else111”when (sel=110000000 ”)else(9)a”zzz”;(10)end a;4、根據(jù)已給出的全加器的（本題 15 分）VHDL 程序，試寫出一個(gè)4 位逐位進(jìn)位全加器的VHDL 程序。

20、library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;entity adder isport (carr:inout std_logic;sum: out std_logic);end adder;architecture adder_arch of adder is beginsum = a xor b xor c;carr = (a and b) or (b and c) or (a and c);end adder_arch;entity

21、full_add isport (a,b: in std_logic_vector (3 downto 0); carr: inout std_logic_vector (4 downto 0); sum: out std_logic_vector (3 downto 0);(5)end full_add;architecture full_add_arch of full_add iscomponent adderport (a,b,c: in std_logic;sum:out std_logic);end component;(10)begincarr(0)=0;u0:adder por

22、t map(a(0),b(0),carr(0),carr(1),sum(0);u1:adder port map(a(1),b(1),carr(1),carr(2),sum(1);u2:adder port map(a(2),b(2),carr(2),carr(3),sum(2);u3:adder port map(a(3),b(3),carr(3),carr(4),sum(3);end full_add_arch;(15)四、 編程(共 50 分，除特殊聲明，實(shí)體可只寫出 PORT 語句，結(jié)構(gòu)體要寫完整)1、用IF語句編寫一個(gè)四選一電路，要求輸入d0d3, s為選擇端，輸出y。(本題10分)

23、entity MUX4 isport(s:in std_logic_vector(1 downto 0);y: out std_logic);end MUX4;(3)architecture behave of MUX4 is beginprocess(s)beginif (s=00) theny=d(0); (4) elsif (s=01) theny=d(1);(5)elsif (s=10) theny=d(2);(6)elsif (s=11) theny=d(3);(7)elsenull;(9)end if;(10)end process;end behave;，要求使能信號 g 低電1

24、 。（本題 10 分）程序（ 10 分）。2、編寫一個(gè)數(shù)值比較器 VHDL 程序的進(jìn)程 （不必寫整個(gè)結(jié)構(gòu)框架）平時(shí)比較器開始工作，輸入信號p = q，輸出equ為 0否則為process(p,q)(2)beginif g=0 then(4)if p = q thenequ_tmp = 0;(6)elseequ_tmp = 1;(8)end if;elseequ_tmp = 1;(10)end if;end process;3、填寫完成一個(gè) 3-8 線譯碼器的真值表（ 5 分），并寫出其 VHDL3-8 譯碼器的真值表ena2a1a0y100000000001100100000010101000

25、0001001011000010001100000100001101001000001110010000001111100000000xxx00000000en tity tri_eight isport(a:in std_logic_vector (2 dow nto 0);en: in std_logic;y:out std_logic_vector (7 downto 0);end tri_eight;architecture a of tri_eight issig nal sel: std_logic_vector (3 dow nto 0);(4) beginsel(0) = a(0); sel(1) = a(1); sel(2) = a(2); sel(3) = en;with sel selecty = 00000001 when 1000,00000010 when 1001,00000100 when